ICs & Semiconductors

Infineon claims industry’s first true 1000A voltage regulator for AI

Tue, Mar 26, 2019

Adding to its high current system chipset portfolio, Infineon claims to offer the industry’s first 16-phase digital PWM multiphase controller.

The XDPE132G5C extends the existing portfolio which enables currents of 500 to 1000A and above for next generation CPUs, GPUs, FPGA and ASICs used in artificial intelligence (AI) and 5G datacomms applications.

It has been introduced as CPU current requirements increase to enable next-generation AI and networking workloads, DC/DC voltage regulators to deliver more than 500A to the load. The XDPE132G5C has a true 16-phase digital PWM engine and an improved advanced transient algorithm to address these high phase count requirements, says Infineon. The true active current sharing between phases enables a reliable, compact and cost-saving design, with no need for extra logic doubler ICs.

The XDPE132G5C offers fine V out setting in 0.625mV increments to meet the demands of ASICs and FPGAs of V out control in less than 1mV steps, seen in communication systems today. The XDPE132G5C also supports auto-restart for communications with options to reduce remote site maintenance following power or system glitches.

The XDPE132G5C is packaged in a 7.0 x 7.0mm 56-pin QFN to accommodate 16 phases. It employs a full digital and programmable load line and is PMBus 1.3/AVS-compliant.

Infineon advises that it can be paired with TDA21475, the thermally efficient integrated current sense power stage, to efficiently deliver over 1000A.

The 70A-rated TDA21475 power stage is housed in a 5.0 x 6.0mm package. It provides efficiency of more than 95 per cent. The exposed top significantly reduces the R th(j-top) from 19 degrees C/W in the over-moulded package to 1.6 degrees C/W. This removes heat from the top of the package, for voltage regulator power density and optimal phase count and footprint. The TDA21475 also offers smart over-current and over-voltage protection and delivers temperature and current information to the XDPE132G5C controller.

The company also offers the IR35223 true 10-phase PWM digital controller. This controller provides a cost-effective option for voltage regulation up to 500 A. The IR35223 is housed in a 6.0 x 6.0mm, 48-pin QFN package and provides advanced transient performance and telemetry features including PMBus 1.3/AVS bus compliance.

http://www.infineon.com/next-gen-processors

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Infineon claims industry’s first true 1000A voltage regulator for AI

Tue, Mar 26, 2019

Adding to its high current system chipset portfolio, Infineon claims to offer the industry’s first 16-phase digital PWM multiphase controller.

The XDPE132G5C extends the existing portfolio which enables currents of 500 to 1000A and above for next generation CPUs, GPUs, FPGA and ASICs used in artificial intelligence (AI) and 5G datacomms applications.

It has been introduced as CPU current requirements increase to enable next-generation AI and networking workloads, DC/DC voltage regulators to deliver more than 500A to the load. The XDPE132G5C has a true 16-phase digital PWM engine and an improved advanced transient algorithm to address these high phase count requirements, says Infineon. The true active current sharing between phases enables a reliable, compact and cost-saving design, with no need for extra logic doubler ICs.

The XDPE132G5C offers fine V out setting in 0.625mV increments to meet the demands of ASICs and FPGAs of V out control in less than 1mV steps, seen in communication systems today. The XDPE132G5C also supports auto-restart for communications with options to reduce remote site maintenance following power or system glitches.

The XDPE132G5C is packaged in a 7.0 x 7.0mm 56-pin QFN to accommodate 16 phases. It employs a full digital and programmable load line and is PMBus 1.3/AVS-compliant.

Infineon advises that it can be paired with TDA21475, the thermally efficient integrated current sense power stage, to efficiently deliver over 1000A.

The 70A-rated TDA21475 power stage is housed in a 5.0 x 6.0mm package. It provides efficiency of more than 95 per cent. The exposed top significantly reduces the R th(j-top) from 19 degrees C/W in the over-moulded package to 1.6 degrees C/W. This removes heat from the top of the package, for voltage regulator power density and optimal phase count and footprint. The TDA21475 also offers smart over-current and over-voltage protection and delivers temperature and current information to the XDPE132G5C controller.

The company also offers the IR35223 true 10-phase PWM digital controller. This controller provides a cost-effective option for voltage regulation up to 500 A. The IR35223 is housed in a 6.0 x 6.0mm, 48-pin QFN package and provides advanced transient performance and telemetry features including PMBus 1.3/AVS bus compliance.

http://www.infineon.com/next-gen-processors

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Image recognition SoC includes deep neural network accelerator

Fri, Mar 01, 2019

An image recognition SoC for automotive applications has been announced by Toshiba Electronics Europe. It implements a deep learning accelerator at 10 times the speed and four times the power efficiency of Toshiba’s earlier heterogeneous multi-core SoC for image recognition which was introduced at the 2015 IEEE International Solid-State Circuits Conference (ISSCC).

It is designed for advanced driver assistance systems (ADAS), such as autonomous emergency braking, which require increasingly advanced capabilities. Implementing them requires an image recognition SoC that can recognise road traffic signs and road situations at high speed with low power consumption.

Deep neural networks (DNN), algorithms modelled after the neural networks of the brain, perform recognition processing more accurately than conventional pattern recognition and machine learning, and is widely expected to be used in automotive applications. However, DNN-based image recognition with conventional processors takes time, as it relies on a huge number of multiply-accumulate (MAC) calculations. DNN with conventional high-speed processors also consumes too much power, adds Toshiba.

 To overcome this, it has developed a DNN accelerator that implements deep learning in hardware. It is defined by three features: parallel MAC units, reduced DRAM access and reduced SRAM access.

The ViscontiTM5 SoC has four processers, each with 256 MAC units to boost DNN processing speed. Conventional SoCs have no local memory to keep temporal data close to the DNN execution unit, they also consume a lot of power accessing local memory and when loading the weight data used for the MAC calculations. In Toshiba’s SoC, SRAM is implemented close to the DNN execution unit, and DNN processing is divided into sub-processing blocks to keep temporal data in the SRAM, reducing DRAM access. Additionally, Toshiba has added a decompression unit to the accelerator. Weight data, compressed and stored in DRAM in advance, are loaded through the decompression unit. This reduces the power consumption involved in loading weight data from DRAM, explains Toshiba.

Finally, conventional deep learning needs to access SRAM after processing each layer of DNN, which consumes too much power. The accelerator has a pipelined layer structure in the DNN execution unit of DNN, allowing a series of DNN calculations to be executed by one SRAM access.

The ViscontiTM5 SoC complies with ISO26262, the global standard for functional safety for automotive applications.

Sample shipments of Toshiba’s image-recognition processor will begin in September 2019.

 http://www.toshiba.semicon-storage.com  

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Ethernet PHYs optimise network performance

Fri, Feb 22, 2019

Two Ethernet physical layer (PHY) transceivers have been introduced by Texas Instruments. They are designed to offer more connectivity options for designers of both space-constrained applications and time-sensitive networks (TSNs).

The DP83825I low-power 10-/100-Mbits per seocnd Ethernet PHY has a 44 per cent smaller package size than competing devices, claims Texas Instruments and provides a 150m cable reach. The DP83869HM is the industry’s only gigabit Ethernet PHY that supports copper and fibre media, and offers high -temperature operation up to 125 degrees C, which enables engineers to leverage the speed and reliability of Gigabit Ethernet connectivity in harsh environments.

The small package, low power consumption and long cable reach of the DP83825I enable designers to reduce the size and cost of compact IP network camera, lighting, electronic point-of-sale and other space-constrained applications without sacrificing network reach, explains Texas Instruments. The high operating temperature of the DP83869HM, as well as its electrostatic discharge (ESD) immunity and support for media conversion, are claimed to help increase performance and design flexibility in factory automation, motor drive and grid infrastructure equipment designs.

Network reach can be expanded while system size and cost can be reduced, with the DP83825I. This is claimed to be the industry’s smallest Ethernet PHY, in a 3.0 x 3.0mm QFN 24-pin package. It also has a long cable reach and helps designers shrink system designs while increasing the physical span of networks, says Texas Instruments. The device’s extended cable reach eliminates the need for Ethernet repeaters, which further reduces operating costs.

The DP83825I reduces thermal loading and power demands for Ethernet connectivity and enables the allocation of power to other critical components within a system by consuming less than 125mW. The device also includes power-saving features such as energy-efficient Ethernet, wake-on-LAN and media access control isolation.

The DP83869HM is claimed to have the industry’s widest temperature range and high ESD immunity. Operating temperature is -40 to +125 degrees C for Gigabit fibre operation and ESD immunity exceeds the 8kV International Electrotechnical Commission 61000-4-2 standard. The DP83869HM helps improve Ethernet system reliability in high-temperature and static-prone industrial environments such as factory floors.

It supports 1000Base-X and 100Base-FX Ethernet protocols and conversion between copper and fibre Ethernet standards, to extend long-distance networks. There is also TSN support through low latency (less than 390 nano seconds total) for both 1000Base-T and 100Base-TX standards.

Evaluation models for both PHYs are available.

http://www.ti.com

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