Intel ships Stratix 10 DX FPGAs to accelerate data centre workloads

FPGAs designed to support Intel Ultra Path Interconnect (UPI), PCI-Express (PCIe) Gen4 x16 and a new controller for Intel Optane technology are shipping from Intel. The Stratix 10 DX FPGAs are designed to boost acceleration of workloads in the cloud and enterprise when used with Intel’s data centre products.

The Stratix 10 DX FPGAs have new interfaces, including the option to support select Intel Optane DC persistent memory dual in-line memory modules (DIMMs). They increase bandwidth and provide coherent memory expansion and hardware acceleration for future Intel Xeon Scalable processors, reveals the company.

Data centre customers are using hardware accelerators, like FPGAs, for more computational speed from server systems running networking and cloud-based applications such as artificial intelligence (AI) training / inferencing or database-related workloads. The effective performance of hardware accelerators depends heavily on the communications bandwidth and latency between one or more server CPUs, available system memory and any attached accelerator, such as a graphics processor unit or application-specific standard products.

Diverting tasks to accelerators frees up CPU cores to become available to work on other higher priority workloads, increasing data centre operator efficiency, says Intel.

Stratix 10 DX FPGAs’ features include a memory controller which supports up to eight Intel Optane DC persistent memory modules per FPGA (up to 4Tbytes of non-volatile memory). There is also 100Gbyte per second Ethernet, HBM2 memory stacks and a quad-core Arm Cortex-A53 processor sub-system with peripherals.

The Stratix 10 DX joins the Stratix 10 GX, Stratix 10 SX SoC FPGAs, Stratix 10 TX and Stratix 10 MX FPGAs.

http://www.intel.com

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LED driver futureproofs with distortion-cancelling technology

Featuring a distortion cancelling input current shaping (ICS) circuit, the HVLED007 AC/DC LED driver enables energy-saving solid-state luminaires to comply with increasingly stringent lighting regulations, says STMicroelectronics.

The HVLED007 implements a peak current mode power factor control (PFC) control optimised for isolated high-power-factor quasi-resonant flyback converters. The ICS ensures an effectively sinusoidal input waveform with very low total harmonic distortion (THD) over the full load and input-voltage range, confirms ST. THD is below five per cent at full load. With near-unity power-factor capability and maximum energy efficiency over 90 per cent, the HVLED007 can be used for a single control IC to address multiple medium- and high-power LED-lighting applications up to 80W.

The HVLED007 is part of the HVLED family of digital ICs for driving LEDs directly from the rectified mains. The members are characterised by integration and support for economical primary-side regulation to lower the bill-of-materials costs and compact circuit size while enhancing system reliability and lighting performance, according to ST.

The electrical parameters of the HVLED007 are specified down to -40 degrees C, allowing use in outdoor lighting including street lighting as well as indoor applications. The totem-pole output stage can source and sink 600mA and 800mA respectively, enabling use in EN61000-3-2 compliant switched-mode power supplies up to 100W in addition to lighting applications. There is also short-circuit, overload, and over-voltage protection integrated in the HVLED007.

The HVLED007 is in production now in the industry-standard SO8 small-outline package.

http://www.st.com

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QuickLogic partners with Nuance Communications for voice recognition

Multi-core, voice-enabled SoCs, embedded FPGA IP, and endpoint AI provider, QuickLogic is partnering with conversational AI and ambient intelligence specialist, Nuance Communications, to deliver low power, wake word and voice command technology for power-sensitive applications, such as hearable and wearable devices.

Nuance’s voice recognition technology and QuickLogic’sEOS S3 voice and sensor processing platform will provide customers an end-to-end, reliable hardware and software voice recognition solution, says QuickLogic.

The low power Nuance voice recognition technology has been integrated with QuickLogic’s advanced EOS Voice and Sensor Processing SoC. The SoC’s architecture is claimed to enable the industry’s most advanced and compute intensive sensor processing capability at a fraction of the power consumption of competing technologies.

The Nuance technology provides the performance and low power consumption required for always-on wake word detection, and specifically supports the Alexa wake-word protocol. Technical enhancements enable it to improve voice recognition accuracy in difficult or noisy environments.

The integrated system supports always-on, always-listening fixed triggers, user defined triggers and phrases, and commands that can be accurately detected in silent to extremely noisy environments.

Scott Haylock, director of product marketing at QuickLogic, explains:”In response to customer demand, and the growing hearables market, we’ve augmented the EOS S3 OPEN Software Platform to include Nuance’s technology. This addition helps QuickLogic address the largest possible product mix of new and existing voice-controlled end-products.”

The EOS S3 platform with integrated Nuance voice processing is available now.

QuickLogic is a fabless semiconductor company that develops low power, multi-core semiconductor platforms and IP for artificial intelligence (AI), voice and sensor processing. It supplies embedded FPGA IP (eFPGA) for hardware acceleration and pre-processing, and heterogeneous multi-core SoCs that integrate eFPGA with other processors and peripherals. The Analytics Toolkit provides sensor algorithms using AI technology.

http://www.quicklogic.com 

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Synopsys claims industry’s first CXL IP for data-intensive SoCs

Low latency and high bandwidth are assured for artificial intelligence (AI), memory expansion and cloud computing, says Synopsys at the introduction of its DesignWare Compute Express Link (CXL) IP.

It is, according to Synopsys, the industry’s first CXL IP for data-intensive system of chips (SoCs). The IP suite consists of controller, PHY, and verification IP for AI, memory expansion, and high-end cloud computing system-on-chips (SoCs). The CXL protocol enables low-latency data communication between the SoC and general-purpose accelerators, memory expanders, and smart I/O devices requiring high-performance, heterogenous computing for data-intensive workloads. The DesignWare CXL IP is compliant with the CXL 1.1 specification and supports all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types to meet specific application requirements.

The CXL IP is built on Synopsys’ DesignWare IP for PCI Express 5.0, which has been adopted by semiconductor companies across all key market segments, reports the company.

“Compute Express Link is a key enabler for next-generation heterogeneous computing architectures, where CPUs and accelerators work together to deliver the most advanced solutions,” said Dr. Debendra Das Sharma, Intel Fellow and director of I/O Technology and Standards at Intel.

Synopsys’ DesignWare CXL Controller helps designers achieve timing closure at 1GHz and provides a robust 512-bit architecture that supports x16 links for maximum CXL bandwidth. The CXL controller offers reliability, availability, serviceability (RAS) capabilities to help maintain data reliability, as well as successfully debug and resolve linkup issues. The 32GTerabytes per second PHY allows more than 36dB channel loss across power, voltage and temperature (PVT) variations for long-reach applications. The VC Verification IP for CXL verifies I/O, memory access, and coherency protocol features with built-in sequences, checks, and coverage for all link configurations up to 16 lanes and 32GTbytes per second data rates. SystemVerilog test suites for CXL accelerate verification closure and are available as source code.

Synopsys’ 32G PHY IP for CXL is available now in 16-, 10-, and 7nm FinFET processes. The CXL Controller and VC Verification IP for CXL are available now.

http://www.synopsys.com/designware

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