Research indicates Pohoiki Beach chip for neural-inspired algortithms

An eight million neuron system, comprised of 64 Phokiki Beach chips, the codename for Loihi chips, is now available to the research community. The neuromorphic system will allow researchers to experiment with Lohi, Intel’s brain-inspired research chip, which applies the principles found in biological brains to computer architectures. Loihi enables users to process information up to 1,000 times faster and 10,000 times more efficiently than CPUs for specialised applications like sparse coding, graph search and constraint-satisfaction problems.

The early results success has led Intel to make Pohoiki Beach available to over 60 ecosystem partners, who will use the system to solve complex, compute-intensive problems, explained Rich Uhlig, managing director of Intel Labs.

Availability means researchers can now efficiently scale up neural-inspired algorithms — such as sparse coding, simultaneous localisation and mapping (SLAM), and path planning — that can learn and adapt based on data inputs.

Intel Labs hopes to scale the architecture to 100 million neurons later this year.

As new complex computing workloads become the norm, there is a growing need for specialised architectures designed for specific applications. This will be achieved by continued process node scaling in the same vein as the power-performance increases achieved by Moore’s Law.

Using the Pohoiki Beach neuromorphic system rather than general purpose computing technologies, Intel hopes to realise gains in speed and efficiency in autonomous vehicles, smart homes and cybersecurity.

“With the Loihi chip we’ve been able to demonstrate 109 times lower power consumption running a real-time deep learning benchmark, compared to a [graphics processor unit] GPU, and five times lower power consumption compared to specialised IoT inference hardware,” said Chris Eliasmith, co-CEO of Applied Brain Research and professor at University of Waterloo. He continued: “As we scale the network up by 50 times, Loihi maintains real-time performance results and uses only 30 per cent more power, whereas the IoT hardware uses 500 per cent more power and is no longer real-time.”

In another research project, Loihi has been used in a neural network that imitates the brain’s underlying neural representations and behaviour. “The SLAM solution emerged as a property of the network’s structure,” explained Konstantinos Michmizos of Rutgers University. “We benchmarked the Loihi-run network and found it to be equally accurate while consuming 100 times less energy than a widely used CPU-run SLAM method for mobile robots,” he said.

Later this year, Intel will introduce an even larger Loihi system, named Pohoiki Springs. Intel’s engineers expect that measurements from these research systems will quantify the gains that are achievable with neuromorphic-computing methods and will clarify the application areas most suitable for the technology. This research paves the way for the eventual commercialisation of neuromorphic technology.

The Intel’s Nahuku boards pictured each contain eight to 32 Intel Loihi neuromorphic chips, interfaced to an Intel Arria 10 FPGA development kit.

(Credit: Tim Herman/Intel Corporation)

http://www.intel.com

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NFC tag allows seamless mobile connectivity

Infineon Technologies claims to have introduced the world’s first certified NFC Type 4B tag. It is claimed to be the first product worldwide certified by the NFC Forum that supports the contactless Type B protocol.

Near field communication (NFC) allows wireless communication between two electronic devices within a distance of approximately 4 cm. NFC tags use this technology to exchange data and to enable contactless payments using smart cards or mobile handsets. NFC tags provide smartphones with reliable data exchange and reference tags for interoperability testing with all types of internationally standardised NFC protocols. This latest NFC reference tag is based on SECORA Pay security, which has been approved under the NFC Forum Certification Program. This confirms their compliance with the Type 4A Tag and the Type 4B Tag.

NFC tags have been generally limited to use cases where security is not deemed to be critical – such as sharing URLs or exchanging business cards. However, they can also be combined with security critical payment applications. Users can activate services via NFC connectivity without having to open an app, and thus instantly connect their mobile handset to, for example, smart devices like wearables or access shared services such as pavement scooters with intuitive connectivity for everyday digital transactions.

The NFC reference tags are based on Infineon’s SPA1.1 module and are pre-loaded with NFC data exchange format (NDEF) files so developers can test a wide variety of smartphones for compliance with ISO/IEC 14443 Type A and Type B.

The Type A and Type B NFC tags are available in pairs.

http://www.infineon.com

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Amplifiers and comparators shrink space requirements

Smaller personal electronics, enterprise, industrial and communications designs can be achieved with the INA185 current-sense amplifier, and open-drain TLV4021 and push-pull TLV4041 comparators, claims Texas Instruments.

The INA185 is claimed to be the industry’s smallest current-sense amplifier in a leaded package and the TLV4021 and push-pull TLV4041, with an internal 1.2 or 0.2V reference, are claimed to be the smallest, most accurate comparators. In addition, says Texas Instruments, pairing the amplifier with one of the comparators produces the smallest, highest performing overcurrent detection solution in the industry.

The INA185 current-sense amplifier achieves more precision in less space, says the company. It is offered in a small-outline transistor (SOT)-563 package (1.6 x 1.6mm or 2.5mm2), making it 40 per cent smaller than the closest competitive leaded packages, says Texas Instruments.

It has a 55 microV input offset that enables higher precision measurements at low currents, and enables the use of lower-value shunt resistors to cut system power consumption. The 350kHz bandwidth and 2.0V/micro second slew rate enable phase-current reproduction to enhance motor efficiency and also save system power.

The matched resistive gain network enables a maximum gain error down to 0.2 per cent, which contributes to robust performance over temperature and process variations. The device’s typical response time of two micro seconds enables fast fault detection to prevent system damage.

The TLV4021 and TLV4041 comparators are available in a small die-size ball grid array (DSBGA) 0.73 x 0.73mm package. Both have an integrated voltage reference which saves board space and supports precise voltage monitoring to optimise system performance.

The comparators can monitor voltages down to 0.2V internal reference and feature a high threshold accuracy of one per cent across a full temperature range from -40 to +125 degrees C. Low 2.5 microA quiescent current delivers extended battery life for smart, connected devices, while a fast propagation delay (as low as 450 nano seconds) reduces latency and enables systems to monitor signals and respond quickly to fault conditions.

When used in combination, the INA185 and the TLV4021 or TLV4041, produce  the smallest, highest-performing overcurrent detection partnership, around 15 per cent smaller and 50 times faster than competitive devices, points out Texas Instruments.

Pairing the amplifier with one of the comparators to support overcurrent detection on rails as high as 26 V delivers more headroom to better manage current spikes, adds Texas Instruments.

TINA-TI SPICE models and reference designs to simulate system designs and predict circuit behaviour when using the INA185 current-sense amplifier and TLV4021 and TLV4041 comparators are available, together with evaluation modules, the INA185EVM and TLV4021-41EVM.

http://www.ti.com

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Renesas announces memory technology for AI

Renesas Electronics has developed an AI accelerator that performs convolutional neural network (CNN) processing at high speeds and low power.  A test chip with this accelerator has achieved the power efficiency of 8.8Tera operations per second per W (TOPS/W), which is the industry’s highest class of power efficiency, reports Renesas. The accelerator is based on the processing-in-memory (PIM) architecture, in which multiply-and-accumulate (MAC) operations are performed in the memory circuit as data is read out from that memory.

To create the new AI accelerator, Renesas developed three technologies. The first is a ternary-valued (-1, 0, 1) SRAM structure PIM technology that can perform large-scale CNN computations. The second is an SRAM circuit to be applied with comparators that can read out memory data at low power. The third is a technology that prevents calculation errors due to process variations in the manufacturing. Together, these technologies achieve a reduction in the memory access time in deep learning processing and a reduction in the power required for the MAC operations. As a result, the accelerator achieves the industry’s highest class of power efficiency while maintaining an accuracy ratio more than 99 per cent when evaluated in a handwritten character recognition test (MNIST), claims Renesas.

Before this development, the PIM architecture was unable to achieve an adequate accuracy level for large-scale CNN computations with single-bit calculations because the binary (0,1) SRAM structure was only able to handle data with values 0 or 1. Additionally, process variations in the manufacturing reduced the reliability of these calculations. The technologies developed by Renesas resolve these issues and can be applied to implement AI chips of the future and e-AI solutions for applications such as wearable equipment and robots that require both performance and power efficiency, says Renesas.

Since introducing the embedded AI (e-AI) concept in 2015, Renesas has defined classes based on the effectiveness of e-AI and applications that are implemented and has been developing e-AI solutions based on four classes: judging the correctness or abnormality of signal waveform data; judging correctness or abnormality using real-time image processing; performing recognition in real time and enabling incremental learning at an endpoint.

https://www.renesas.com 

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