Intel has introduced two x86 core architectures – the Efficient-core and Performance-core microarchitectures.
The Efficient-core microarchitecture, previously code-named Gracemont, is designed for throughput efficiency, enabling scalable multi-threaded performance for multi-tasking. It is, says Intel, the company’s most efficient x86 microarchitecture for multi-core workloads with a workload that can increase with the number of cores.
It also delivers a wide frequency range. The microarchitecture allows Efficient-core to run at low voltage to reduce overall power consumption, while creating the power headroom to operate at higher frequencies. As a result, the microarchitecture can ramp up performance for more demanding workloads.
Efficient-core include a variety of advances to optimise workloads while conserving processing power and to improve instruction per cycle (IPC) rates. For example, it has a 5,000 entry branch target cache for more accurate branch prediction and a 64kbyte instruction cache to keep useful instructions close without expending memory subsystem power.
It also includes Intel’s first on-demand instruction length decoder that generates pre-decode information and Intel’s clustered out-of-order decoder to decode up to six instructions per cycle while maintaining energy efficiency. Other features include a wide back end with five-wide allocation and eight-wide retire, 256 entry out-of-order window and 17 execution ports.
Technology advanced include Intel Control-flow Enforcement Technology and Intel Virtualization Technology Redirection Protection. There Efficient-core microarchitecture also has the AVX ISA and new extensions to support integer artificial intelligence (AI) operations.
Intel says that the Efficient-core achieves 40 per cent more performance at the same power, compared with the Skylake CPU core, in single-thread performance. Alternatively, it can deliver the same performance while consuming 40 per cent less power. For throughput performance, four Efficient-cores offer 80 per cent more performance while still consuming less power than two Skylake cores running four threads or the same throughput performance while consuming 80 per cent less power.
The second microarchitecture to be launched Intel Architecture Day is Performance-core (previously code-named Golden Cove). This microarchitecture is the highest performing CPU core built by Intel and is designed for speed with low latency and single-threaded application performance. It has been introduced to address the fact that workloads are growing in terms of code footprint, demand more execution capabilities and have growing data sets and data bandwidth requirements. Performance-core microarchitecture is intended to provide “a significant boost in general purpose performance and better support for large code footprint applications,” said the company.
The Performance-core features a wider, deeper and smarter architecture than earlier microarchitectures with six decoders, eight-wide micro-op cache, six allocation and 12 execution ports. It also has bigger physical register files and deeper re-order buffer with 512 entry.
Other advances are improved branch prediction accuracy, reduced effective L1 latency and full write predictive bandwidth optimisations in L2.
Other features which help it to lower latency and advance single-threaded application performance are a Geomean improvement of around 19 per cent across a range of workloads over current 11th Gen Intel Core processor architecture (Cypress Cove) at ISO frequency.
There is also more parallelism and an increase in execution parallelism. For deep learning inference and training, there are Intel Advance Matrix Extension to accelerate AI. There is also dedicated hardware and new instruction set architecture to perform matrix multiplication operations “significantly faster”. The reduced latency is accompanied by increased support for large data and large code footprint applications.
