Synopsys packages controller, PHY and verification IP in HBM3 suite
To accelerate development of 2.5D multi-die package systems, Synopsys offers what is claims is the industry’s first complete HBM3 IP and verification for high-performance computing, artificial intelligence (AI) and graphics SoCs.
The DesignWare HBM3 controller and PHY IP are built on silicon-proven HBM2E IP, and use Synopsys’ interposer technology to enable high memory bandwidth at up to 921Gbytes per second.
The verification solution includes verification IP with built-in coverage and verification plans, off-the-shelf HBM3 memory models for ZeBu emulation, and HAPS prototyping system, accelerates verification from HBM3 IP to SoCs.
3DIC Compiler multi-die design offers architectural exploration, implementation and system-level analysis. The DesignWare HBM3 controller IP supports a variety of HBM3-based systems with flexible configuration options. The controller minimises latency and optimises data integrity with advanced RAS (reliability, availability, serviceability) features that include error correction code, refresh management and parity.
The DesignWare HBM3 PHY IP in 5.0nm process, is available as pre-hardened or customer configurable PHY. It operates at up to 7200Mbits per second per pin and is claimed to “significantly” improve power efficiency and supports up to four active operating states enabling dynamic frequency scaling. The DesignWare HBM3 PHY uses an optimised micro bump array to help minimise area. The support for interposer trace lengths gives designers more flexibility in the PHY placement without impacting performance.
Synopsys Verification IP for HBM3 uses next-generation native SystemVerilog Universal Verification Methodology architecture to integrate existing verification environments and run a greater number of tests, accelerating time to first test. The off-the-shelf HBM3 memory models for ZeBu emulation and HAPS prototyping system enable RTL and software verification for higher levels of performance.
The suite has already been welcomed by customers. “Micron is committed to empowering the world’s most advanced computing systems with the industry’s highest performing solutions. HBM3 will deliver the memory bandwidth critical to enabling the next generation of high-performance computing and artificial intelligence systems,” said Mark Montierth, Micron vice president and general manager of High-Performance Memory and Networking.
“SK hynix, a leading global semiconductor manufacturer, continues to invest in developing next-generation memory technologies, including HBM3 DRAMs, to meet the exponential growth in workloads for AI and graphics applications,” said Cheol Kyu Park, vice president, HBM Product Champion and head of DRAM Product Engineering at SK hynix. “We will leverage our long-standing relationship with Synopsys to provide our mutual customers with fully-tested and interoperable HBM3 solutions that can maximize memory performance, capacity and throughput.”
“Our recent collaboration with Synopsys, leveraging Synopsys’ HBM2E IP on 5nm process and integrated full-system multi-die design platform, will extend to include the new DesignWare HBM3 IP and verification solutions. As a result, our customers can achieve higher memory performance and capacity in SoCs requiring the upcoming HBM3 specification,” added Yutaka Hayashi, vice president of Data Center & Networking Business Unit at Socionext
The DesignWare IP includes logic libraries, embedded memories, PVT sensors, embedded test, analogue IP, interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems.
The DesignWare HBM3 Controller, PHY, and Verification IP as well as the ZeBu emulation memory model, HAPS prototyping system and 3DIC Compiler are available now.
