Microchip’s 1.2V clock buffers bridge SoCs and FPGAs to higher voltages
Microchip Technology has introduced the SY757xx family, a portfolio of 1.2V-output LVCMOS clock buffers. The new devices simplify system design by eliminating the need for traditional discrete-component implementations while delivering ultra-low additive jitter performance. To provide flexibility for supporting legacy board power supplies and different clock-source voltage levels, the devices support a broad range of supply voltage (VDD) and a wide operating frequency range. The SY757xx family enables ultra-low additive jitter clock distribution while maintaining the high clock resolution and signal integrity required for today’s high-speed FPGA, SoC and CPU platforms.
Microchip’s SY757xx family strengthens the clock buffer’s role as a critically important SoC and FPGA interface for clock distribution and clock fanout functionality in application platforms where signal integrity is paramount. These platforms demand high-speed parallel processing, hardware reconfigurability, low latency and efficient real-time computing.
These capabilities are required for applications ranging from embedded vision and video processing to AI/ML acceleration, industrial control and IoT, networking and communications, and signal processing and embedded systems.
Launching three products in production and eight that are sampling in limited volumes, the family spans a wide array of configurations in three space-saving packaging options. The devices protect against clock distortion across a 0 Hz to 250 MHz frequency spectrum while also offering a broad range of power supply input and output options across the 1.2V to 3.3V voltage-translation input range. This includes a single-chip option that reliably interconnects 3.3V components to FPGAs and SoCs with a 1.2V clock signal requirement. Additive jitter is as low as 26 femtoseconds (fs).
Compared to traditional discrete component solutions for these FPGA and SoC applications, the Microchip buffers simplify design and reduce bill-of-materials costs while helping to optimise AC coupling and biasing and maintain signal integrity. Voltage dividers using discrete components may not provide adequate design margin and can degrade signal integrity by causing duty-cycle distortion.
Microchip clock buffers complement the company’s range of flash-based FPGAs and SoC FPGAs spanning ultra-low density to mid-range density devices. These and other Microchip products that range from microcontrollers and analog components to power management, timing, connectivity and memory devices are pre-engineered and validated to enable a simplified, lower-risk and more holistic approach to system design.
The other eight SY757xx family members bridge to 1.2V-to-1.8V LVCMOS outputs from a choice of single-ended 1.2V to 3.3V LVCMOS inputs, single-ended 1.2V to 1.8V LVCMOS inputs, or differential 1.8V to 3.3V inputs. There are also options for an output-enabled (OE) fanout buffer. All the sampling devices are housed in 8-pin VDFN packages.
