ICs & Semiconductors

Microcontrollers have dual-core performance

Wed, Jun 05, 2019

Claimed to be the industry’s highest-performing Arm Cortex-M general-purpose microcontrollers, the STM32H7 devices combined dual-core operation with power-saving features and enhanced cyber protection, says STMicroelectronics.

The microcontrollers use a 480MHz version of the Cortex-M7, the highest performing member of the Cortex-M family and add a 240MHz Cortex-M4 core. The microcontrollers are based on ST’s smart architecture and have its efficient L1 cache and adaptive real-time ART Accelerator, to set new speed records at 1327 DMIPS and 3224 CoreMark executing from embedded Flash.

ST’s Chrom-ART Accelerator boosts graphics performance, while each core operates in its own power domain and can be turned off individually when not needed, to maximise power efficiency.

Developers can upgrade existing applications using the two cores, for example, adding a sophisticated user interface to a motor drive, formerly hosted on a single-core Cortex-M4, by migrating legacy code to the STM32H7 Cortex-M4 with the new graphics user interface (GUI) running on the Cortex-M7. Another example is to boost application performance by offloading intensive workloads such as neural networks, checksums, DSP filtering, or audio codecs.

The dual-core architecture also helps simplify code development and accelerate time to market in projects where user-interface code may be developed separately from real-time control or communication features.

STM32H7 microcontrollers have pre-installed keys and native secure services including Secure Firmware Install (SFI). SFI lets customers order standard products anywhere in the world and have the encrypted firmware delivered to an external programming company without exposing unencrypted code. Other protection includes built-in support for Secure Boot and Secure Firmware Update (SB-SFU) to protect over the air (OTA) upgrades and patches.

The STM32H7 microcontrollers have up to 2Mbyte flash and 1Mbyte SRAM on-chip to simplify the design of smart objects in industrial, consumer, and medical applications with real-time performance or artificial intelligence (AI) processing requirements. The Cortex-M7 level 1 cache and parallel and serial memory interfaces offer unlimited and fast access to external memory, adds ST.

The microcontrollers are also characterised by error code correction (ECC) for all flash and RAM to increase safety, multiple advanced 16-bit ADCs, external ambient-temperature range up to 125 degrees C allowing use in severe environments, an Ethernet controller and multiple FD-CAN controllers and ST’s high-resolution timer for generating precision waveforms.

STM32H7 dual-core microcontrollers are entering production and samples are available now.

http://www.st.com

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Quick-start software to develop embedded ADAS

Tue, Jun 04, 2019

Software has been developed specifically to use the hardware accelerators in Renesas Electronics’ R-Car V3H SoC for advanced driver assistance systems (ADAS) in automotive design.

To accelerate the development of ADAS, the Perception Quick Start software,  based on the R-Car V3H SoC delivers reference software for camera obstacle detection (COD), lidar obstacle detection (LOD), and road feature detection (RFD), deemed as three key recognition areas for sensor-based Level 2+ autonomous vehicle systems.

The COD reference software uses convolutional neural network (CNN) IP, a computer vision engine (CV-E), and image rendering (IMR) technology to detect 2D objects such as cars, trucks, buses, and pedestrians. It achieves approximately 30 frames per second.

The LOD software uses CNN-IP and CV-E to detect 3D objects, including cars and trucks. The LOD achieves approximately 15 frames per second with 3D bounding boxes at 50m.

The RFD reference software uses CNN-IP, CV-E, IMR, and a versatile pipeline engine (IMP) to identify drivable free space, lanes (crossable and uncrossable), road boundaries, and distances to lanes and nearest objects to support NCAP 2020. The RFD achieves approximately 30 frames per second.

The R-Car V3H SoCs deliver a combination of high computer vision performance and artificial intelligence (AI) processing at low power levels, for automotive front cameras in Level 2+ autonomous vehicles. To advance recognition technology, Renesas designed the SoCs with dedicated hardware accelerators for key algorithms including convolutional neural networks, dense optical flow, stereo disparity, and object classification. The Perception software provides an end-to-end pipeline reference for developers working with these complex accelerators which are both cost-effective and power-efficient, thereby allowing customers to advance an application design even if they have limited experience at using the accelerators. The reference software covers input from sensor or recorded data, all stages of processing and display output on a screen.

“Specialised hardware accelerators play an essential role in achieving the computer vision performance and accuracy required in embedded ADAS and autonomy applications while still meeting stringent in-vehicle power consumption limits,” said Tim Grai, director or automotive advanced systems innovation department, Renesas. “However, the complexity of these accelerators can present a steep learning curve. With the Perception Quick Start software, we are able to offer a set of application software along with the underlying primitives to simplify the use of these complex accelerators needed to achieve embedded ADAS.”

Renesas will demonstrate the Perception software at TU-Automotive Detroit (Booth C190, 5-6 June, Novi, Michigan, USA).

http://www.renesas.com

> Read More

Quick-start software to develop embedded ADAS

Tue, Jun 04, 2019

Software has been developed specifically to use the hardware accelerators in Renesas Electronics’ R-Car V3H SoC for advanced driver assistance systems (ADAS) in automotive design.

To accelerate the development of ADAS, the Perception Quick Start software,  based on the R-Car V3H SoC delivers reference software for camera obstacle detection (COD), lidar obstacle detection (LOD), and road feature detection (RFD), deemed as three key recognition areas for sensor-based Level 2+ autonomous vehicle systems.

The COD reference software uses convolutional neural network (CNN) IP, a computer vision engine (CV-E), and image rendering (IMR) technology to detect 2D objects such as cars, trucks, buses, and pedestrians. It achieves approximately 30 frames per second.

The LOD software uses CNN-IP and CV-E to detect 3D objects, including cars and trucks. The LOD achieves approximately 15 frames per second with 3D bounding boxes at 50m.

The RFD reference software uses CNN-IP, CV-E, IMR, and a versatile pipeline engine (IMP) to identify drivable free space, lanes (crossable and uncrossable), road boundaries, and distances to lanes and nearest objects to support NCAP 2020. The RFD achieves approximately 30 frames per second.

The R-Car V3H SoCs deliver a combination of high computer vision performance and artificial intelligence (AI) processing at low power levels, for automotive front cameras in Level 2+ autonomous vehicles. To advance recognition technology, Renesas designed the SoCs with dedicated hardware accelerators for key algorithms including convolutional neural networks, dense optical flow, stereo disparity, and object classification. The Perception software provides an end-to-end pipeline reference for developers working with these complex accelerators which are both cost-effective and power-efficient, thereby allowing customers to advance an application design even if they have limited experience at using the accelerators. The reference software covers input from sensor or recorded data, all stages of processing and display output on a screen.

“Specialised hardware accelerators play an essential role in achieving the computer vision performance and accuracy required in embedded ADAS and autonomy applications while still meeting stringent in-vehicle power consumption limits,” said Tim Grai, director or automotive advanced systems innovation department, Renesas. “However, the complexity of these accelerators can present a steep learning curve. With the Perception Quick Start software, we are able to offer a set of application software along with the underlying primitives to simplify the use of these complex accelerators needed to achieve embedded ADAS.”

Renesas will demonstrate the Perception software at TU-Automotive Detroit (Booth C190, 5-6 June, Novi, Michigan, USA).

http://www.renesas.com

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Ethernet PHY combines security engine with Tbit capacity

Fri, May 31, 2019

Microchip claims to have developed the industry’s first Tbit-scale Ethernet PHY that enables the highest-density 400GbE and FlexE connectivity.

The META-DX1 family of Ethernet physical layer (PHY) devices enables telecomms service providers to build networks using routing and switching to reduce cost, optimise bandwidth and increase capacity. The META-DX1 also integrates the Media Access Control Security (MACsec) security engine.

The device, developed by Microchip’s subsidiary, Microsemi, combines Ethernet ports from 1Gigabit Ethernet (GbE) to 400GbE, Flexible Ethernet (FlexE), Media Access Control Security (MACsec) link encryption and nanosecond timestamping accuracy. Its Tbit capacity is designed to address the industry transition from 100GbE to 400 GbE to support traffic within hyperscale data centres. This traffic volume is expected to quadruple by 2021 (source: Cisco’s Global Cloud Index), with data centre-to-data centre traffic growing at more than a 30 per cent cumulative annual growth rate (CAGR).

The META-DX1 enables line cards to quadruple in capacity, from 3.6Tbits per second to 14.4Tbits per second with 36 ports of 400GbE or 144 ports of 100GbE.

The MACsec engine secures traffic leaving the data centre or enterprise premises. FlexE enables both cloud and telecomms service providers to reduce capex by optimally configuring links beyond today’s fixed-rate Ethernet so they can use low-cost, high-volume optics, while meeting the increasing capacity requirements. Combining the MACsec and FlexE in one device, meets the next phase of capacity scaling in data centre interconnect (DCI) buildouts, adds Microchip.

The META-DX1 is further differentiated in the market with the addition of integrated flexible crosspoint switching, which makes it easier for OEMs to navigate the market transition from 25Gbits per second psnon return to zero (NRZ) and 56Gbits per second pulse amplitude modulation (PAM) -based architectures by enabling them to support a single design or device for both 100GbE (QSFP28) and 400GbE (QSFP-DD) optics. Timestamping is also provided with nanosecond-level accuracy on every port to ensure network builds will meet the challenging timing requirements of 5G mobile basestation deployments.

Initial META-DX1 family members will sample during Q3 2019. All devices are hardware-compatible and supported by the same software developer’s kit.

http://www.microchip.com

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