Synopsys claims industry’s first CXL IP for data-intensive SoCs

Low latency and high bandwidth are assured for artificial intelligence (AI), memory expansion and cloud computing, says Synopsys at the introduction of its DesignWare Compute Express Link (CXL) IP.

It is, according to Synopsys, the industry’s first CXL IP for data-intensive system of chips (SoCs). The IP suite consists of controller, PHY, and verification IP for AI, memory expansion, and high-end cloud computing system-on-chips (SoCs). The CXL protocol enables low-latency data communication between the SoC and general-purpose accelerators, memory expanders, and smart I/O devices requiring high-performance, heterogenous computing for data-intensive workloads. The DesignWare CXL IP is compliant with the CXL 1.1 specification and supports all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types to meet specific application requirements.

The CXL IP is built on Synopsys’ DesignWare IP for PCI Express 5.0, which has been adopted by semiconductor companies across all key market segments, reports the company.

“Compute Express Link is a key enabler for next-generation heterogeneous computing architectures, where CPUs and accelerators work together to deliver the most advanced solutions,” said Dr. Debendra Das Sharma, Intel Fellow and director of I/O Technology and Standards at Intel.

Synopsys’ DesignWare CXL Controller helps designers achieve timing closure at 1GHz and provides a robust 512-bit architecture that supports x16 links for maximum CXL bandwidth. The CXL controller offers reliability, availability, serviceability (RAS) capabilities to help maintain data reliability, as well as successfully debug and resolve linkup issues. The 32GTerabytes per second PHY allows more than 36dB channel loss across power, voltage and temperature (PVT) variations for long-reach applications. The VC Verification IP for CXL verifies I/O, memory access, and coherency protocol features with built-in sequences, checks, and coverage for all link configurations up to 16 lanes and 32GTbytes per second data rates. SystemVerilog test suites for CXL accelerate verification closure and are available as source code.

Synopsys’ 32G PHY IP for CXL is available now in 16-, 10-, and 7nm FinFET processes. The CXL Controller and VC Verification IP for CXL are available now.

http://www.synopsys.com/designware

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Power Integrations introduces GaN to LYTSwitch drivers

The latest members of Power Integrations’ LED driver ICs, the LYTSwitch-6 family, use PowiGaN technology to enable designs that deliver up to 110W with 94% conversion efficiency using a simple, flexible flyback topology.

The high efficiency eliminates the need for heatsinks, reducing ballast size, weight and cooling airflow requirements, says Power Integrations. The 750V PowiGaN primary switches provide very low RDS (on) and reduced switching losses, increasing power conversion efficiency by up to three per cent compared to conventional solutions and reducing wasted heat by more than one-third.

LYTSwitch-6 ICs with PowiGaN technology employ lossless current sensing. They retain existing LYTSwitch-6 characteristics, such as fast transient response for cross regulation for parallel LED strings without the need for additional regulator hardware, and flicker-free system operation, says the company. This allows simple implementation of a pulse width modulation (PWM) dimming interface.

The LYTSwitch-6 ICs with PowiGaN technology enable designs up to 110W for smart residential and commercial fixtures and low-profile ceiling troffers. The high power density enables reduced height and weight, which is vital for space-constrained and sealed ballast applications.

The GaN-based LYTSwitch-6 LED-driver ICs are available now. A reference design (DER-801) is also available, describing a 100W three-way dimming LED ballast.

Power Integrations specialises in semiconductor technologies for high-voltage power conversion, with products that are key building blocks in the clean-power ecosystem, enabling the generation of renewable energy as well as the efficient transmission and consumption of power in applications ranging from mW to MWs.

http://www.power.com

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ON Semiconductor uses PoE to meet IoT endpoints’ power demands

Using the new IEEE 802.3bt standard, Power over Ethernet (PoE) can be used to deliver high-speed connectivity up to 90W of power over local area network (LAN) connections. ON Semiconductor has announced that controllers and MOSFETs not only support the new standard power limit, but extends it further to 100W for systems including telecommunications and digital signage.

The IEEE 802.3bt standard for PoE enables more sophisticated endpoints operating across larger networks, explains ON Semiconductor. The IEEE 802.3bt standard optimises energy management through the new Autoclass feature, which enables powered devices (PDs) to communicate specific power needs to the power sourcing equipment (PSE). This in turn allows each PSE to allocate just the right amount of power to each PD, maximising both the available energy and bandwidth.

Three times the power is available with IEEE 802.3bt (90W, compared to the 30W provided by the IEEE 802.at standard, or PoE+). IEEE 802.3bt can provide both power and connectivity to new applications that would otherwise require a dedicated and typically off-line power source. PoE will simplify network topologies and provide a more robust plug-and-play user experience, explains ON Semiconductor.

ON Semiconductor offers the NCP1095 and NCP1096 interface controllers. Both incorporate all of the features needed to implement a PoE interface, including detection, auto-classification and current limiting. The controllers employ either an external (NCP1095) or internal (NCP1096) hot-swap FET. The integrated hot-swap FET in the NCP1096 features the lowest on-resistance available in a Type 3 or Type 4 PoE controller

The controllers are complemented by the NCP1566 DC/DC controller, the FDMC8622 single MOSFET and the FDMQ8203 and FDMQ8205A GreenBridge Quad MOSFETs. These have been developed to provide a more efficient alternative to a diode bridge in PoE applications. Together, these devices enable highly efficient PoE interfaces with up to the standard limit of 90W or to a proprietary 100W.

The company believes it offers a complete family of IEEE 802.3bt-compliant products, to make the technology more accessible and enable more connected devices with guaranteed interoperability.

“PoE is one of the fastest-growing markets for power semiconductors today, with a compound average unit growth rate of 14 per cent expected from 2017 through to 2022,” said Kevin Anderson, senior analyst, power semiconductors at business information provider IHS Markit. “The additional power-delivery capability defined in IEEE 802.3bt enables new applications, such as higher-powered connected lighting, networked high-resolution surveillance cameras and high-performance wireless access points.”

http://www.onsemi.com

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GigaDevice claims a first for open source RISC-V based 32-bit mcu

Believed to be the world’s first open source RISC-V based GD32V series 32-bit general purpose microcontroller (MCU), the GD32 family is announced by GigaDevice. The company says it offers tool chain support from MCU to software libraries and development boards, creating a strong RISC-V development ecosystem.

The first product line in the family is the GD32VF103 series RISC-V MCU. It is designed for mainstream development, says GigaDevice. There are 14 models, including QFN36, LQFP48, LQFP64 and LQFP100, compatible with existing GD32 MCUs in software development and pin packaging.

According to GigaDevice, the design accelerates the development cycle between GD32’s Arm core and RISC-V core products, making product selection and code porting flexible and simple. The GD32VF103 devices are specifically targeted for embedded applications ranging from industrial control, consumer electronics, IoT, edge computing to artificial intelligence and deep learning.

The GD32VF103 MCU series adopts the Bumblebee processor core based on the open source RISC-V instruction set architecture, jointly developed by GigaDevice and Nuclei System Technology. The Bumblebee core uses a 32-bit RISC-V open source instruction set architecture and supports custom instructions to optimise interrupt handling. It is equipped with a 64-bit wide real-time timer and can also generate timer interrupts defined by the RISC-V standard, with support of dozens of external interrupt sources, while possessing 16 interrupt levels and priorities, interrupt nesting and fast vector interrupts processing mechanism.

The low-power management unit can support two-levels of sleep mode. The core supports standard JTAG interfaces and RISC-V debug standards for hardware breakpoints and interactive debugging. The Bumblebee core supports the RISC-V standard compilation tool chain, as well as Linux/Windows graphical integrated development environment.

The core is designed with a two-stage variable-length pipeline microarchitecture with a streamlined dynamic branch predictor and instruction pre-fetch unit. The performance and frequency of the traditional architecture three-stage pipeline can be achieved at the cost of the two-stage pipeline, achieving industry-leading energy efficiency and cost advantages, claims GigaDevice.

The GD32VF103 MCU operates at up to 153DMIPS at the highest frequency and under the CoreMark test achieves 360 performance points. This is a 15 per cent performance improvement compared to the GD32 Cortex-M3 core. Dynamic power consumption is reduced by 50 per cent and the standby power consumption is reduced by 25 per cent, adds the company.

The GD32VF103 series RISC-V MCUs provide a processing frequency of 108MHz, 16kbyte to 128kbyte of on-chip flash and 6 to 32kbyte of SRAM cache, equipped with the gFlash patented technology, which supports high-speed core accesses to flash in zero wait time. The core also includes a single-cycle hardware multiplier, hardware divider and acceleration unit for advanced computing and data processing challenges.

The chip is powered by 2.6 to 3.6V and the I/O ports can withstand 5V voltage level. It is equipped with a 16-bit advanced timer supporting three-phase PWM complementary outputs and Hall acquisition interface for vector control. It also has up to four 16-bit general-purpose timers, two 16-bit basic timers, and two multi-channel DMA controllers. The interrupt controller (ECLIC) provides up to 68 external interrupts and can be nested with 16 programmable priority levels to enhance the real-time performance of high-performance control.

Peripheral resources include up to three USART, two UART, three SPI, two I2C, two I2S, two CAN2.0B, one USB 2.0 FS OTG and an External Bus Expansion Controller (EXMC). The I2C interface supports Fast Plus (Fm+) mode with frequencies up to 1MHz (1Mbits per second), which is two times faster than the previous speed, says GigaDevice. The SPI also supports four-wire system and more transmission modes, including the easy expansion to Quad SPI for high-speed NOR Flash accesses. The USB 2.0 FS OTG interface provides multiple modes such as device, host, and OTG, while the EXMC connects to external memory such as NOR Flash and SRAM.

The GD32VF103 series RISC-V MCUs also integrate two 12-bit high-speed ADCs with sampling rates up to 2.6Msamples per second, provides up to 16 reusable channels, supports 16-bit hardware oversampling filtering and resolution configurability and it has two 12-bit DAC. Up to 80 per cent of GPIOs have optional features and support port remapping.

http://www.gigadevice.com

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