ICs & Semiconductors Archives - Page 190 of 227

IP with 112G Ethernet PHY targets hyperscale data centre SoCs

Thu, Sep 26, 2019

Enabling true long reach channels for 800G networking applications, Synopsys has introduced the DesignWare 112G Ethernet PHY on TSMC’s N7 process.

The DesignWare 112G Ethernet PHY IP on TSMC’s N7 process supports true long reach channels for up to 800G networking applications. It is based on Synopsys’ silicon-proven 56G Ethernet PHY available in multiple FinFET processes and delivers PAM-4 signalling for more than 35dB channel loss across optical, copper cables, and backplane interconnects.

The PHY’s transmit phase-locked loop architecture allows independent, per lane data rates for a broad range of high-throughput protocols and applications. To maximise bandwidth and beachfront density, the PHY’s layout allows square macros to be placed in a multi-row structure and along all edges of the die.

Synopsys offers a routing feasibility study, packages substrate guidelines, signal and power integrity models and thorough crosstalk analysis.

The 112G Ethernet PHY incorporates Synopsys’ data converters and implements power scaling techniques for up to 20 per cent power reduction in low-loss channels. Test features, including embedded bit-error rate tester and internal eye monitor, provide on-chip testability and visibility into channel performance. The 112G Ethernet PHY operates across voltage and temperature variations using continuous calibration and adaptation algorithms.

The DesignWare 112G Ethernet PHY for TSMC’s N7 process is scheduled to be available in Q1 of 2020.

DesignWare IP from IP for SoC designs provider, Synopsys, includes logic libraries, embedded memories, embedded test, analogue IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development, and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems.

Synopsys is the Silicon to Software partner for companies developing electronic products and software applications. The company has a long history in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Customers are SoC designers creating advanced semiconductors, or a software developer writing applications that require high security and quality.

http://www.synopsys.com

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HD LCD video controller has MIPI-CSI2 input for parking assist

Wed, Sep 25, 2019

Claimed to be the first full HD 1080p LCD video controller to include a four-lane MIPI-CSI2 input, the RAA278842 LCD video controller’s four-lane (or dual two-lane) MIPI-CSI2 input supports up to 1Gbit per second per lane. This allows it to interface with the latest generation of automotive cameras, application processors and graphics processors, explains Renesas Electronics. The controller also supports a 150 MHz single-channel OpenLDI interface and a variety of video interfaces and LCD panel sizes with resolutions up to 1920 x 1080.

The RAA278842 can be used for automotive central infotainment displays (CIDs) and head units, instrument clusters, head-up displays (HUDs) and mirror replacement display applications for advanced driver assistance systems (ADAS).

“The RAA278842 LCD video controller helps automotive system manufacturers develop versatile and reliable display systems that provide superior HMI graphics for analogue and digital video content,” said Niall Lyne, senior director, automotive mixed-signal/power and video, Renesas Electronics. “Our strong heritage in video signal processing for backup cameras along with highly differentiated new technology is valued by automakers and Tier-1 suppliers worldwide,” he said.

The RAA278842 LCD video controller has 10-bit per colour processing built into the image enhancement engine to provide near-zero latency, high quality video. Integrated video diagnostics detect if the incoming video is frozen or corrupted and can provide a direct path for the rear camera video to be displayed on the LCD. This significantly improves rear camera display reliability, explains Renesas, claiming that it virtually eliminates the possibility of a software-related problem causing the rear camera video to be displayed incorrectly or not at all. The RAA278842 can display the camera image on an LCD in less than 500 milliseconds, addressing the fast boot requirement of many OEMs. The EEPROM/SPI flash fast boot allows register programming without requiring an external microcontroller

The RAA278842 with MIPI-CSI2 output and the RAA278843 with traditional BT.656 output, work with the system’s main processor to monitor the camera and the video data coming from the SoC or graphics processor unit (GPU). After vehicle ignition, while the instrument cluster boots up, the RAA27884x controller can display the carmaker’s logo or live camera video. The controller’s on-screen display feature can also simulate warning lamp checks in an instrument cluster application.

Both controllers enable compliance with FMVSS-111, requiring the blind spot area behind the vehicle is displayed in less than two seconds after the driver places the vehicle in reverse gear.

Proprietary input switching eliminates flicker when switching between sources, claims Renesas and the AEC-Q100 Grade-2 qualified devices are specified for operation from -40 to +105 degrees C

The RAA278842 and RAA278843 can be combined with Renesas’ R-Car SoC family, RH850 MCU family, and RL78 MCU family, as well as the ISL78302 dual LDO, ISL78322 dual 2A/1.7A synchronous buck regulator, and ISL78228 dual 800mA synchronous buck regulator to provide power rails for the RAA27884x and other ICs on the automotive infotainment system board.

Mass production quantities of the RAA278842 with MIPI-CSI2 output are available now in a 14 x 14mm, 128-lead LQFP package.

Mass production quantities of the RAA278843 with BT.656 output are available now in a 14mm x 14mm, 128-lead LQFP package.

http://www.renesas.com

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Clock generators, buffers and PCIe clocks and buffers are AEC-Q100-qualified

Tue, Sep 24, 2019

To meet the demanding clocking needs of in-vehicle systems, Silicon Labs believes it now offers the industry’s broadest portfolio of automotive grade timing solutions, as it introduces AEC-Q100-qualified timing devices, the Si5332 any-frequency programmable clock generators, Si5225x PCIe Gen1/2/3/4/5 clocks, Si5325x PCIe buffers and Si5335x fanout clock buffers.

These timing devices help automotive OEMs and Tier 1 suppliers simplify clock tree design, reduce system points of failure, increase system reliability and optimise the performance of high-speed serial data transfer. The timing devices target automotive camera sub-systems, radar and lidar sensors, advanced driver assistance systems (ADAS), autonomous driving control units, driver monitoring cameras, infotainment systems, Ethernet switches, and GPS and 5G connectivity.

Rather than using more quartz-based components to satisfy a growing list of timing requirements, developers now have the option to simplify their clock tree designs and increase system reliability using the company’s automotive-grade low-jitter, any-frequency clock generators and buffers.

Quartz crystal and oscillator timing devices can be prone to shock and vibration failure as well as start-up issues, explains Silicon Labs. Clocking requirements increase in demand as automotive infotainment platforms continue to adopt new features and ADAS systems increase complexity and data acquisition rates.

Automotive in-vehicle applications require a higher operating temperature range (Automotive Grade 2, -40 to +105 degrees C) and qualification to AEC-Q100 automotive standards.

The Si5332 clock leverages Silicon Labs’ MultiSynth technology to provide any-frequency, any-output clock synthesis with more than 60 per cent lower jitter than competing automotive clocks, says the company. Supporting up to eight clock outputs, selectable signal formats per output clock (LVDS, LVPECL, HCSL, LVCMOS) and independent 1.8-3.3V VDDO, the Si5332 clock interfaces to a range of FPGAs, ASICs, Ethernet switches/PHYs, processors, GPUs, SoCs, and PCIe Gen1/2/3/4/5 and NVLink SerDes. Clock synthesis, clock distribution and format/level translation are consolidated on-chip, enabling optimised single-IC clock tree solutions for automotive designs.

The Si5332 clock generators and Si5335x clock buffers are configurable and customisable using Silicon Labs’ flexible ClockBuilder Pro software, enabling developers to create optimised solutions that exactly match specific clock tree requirements, with samples shipping in less than two weeks.

Samples and production quantities of automotive grade Si5332 clock generators, Si5225x PCIe clocks, Si5325x PCIe buffers and Si5335x clock buffers are available now in 32-QFN and 40-QFN package options.

Evaluation boards (EVBs) for automotive grade timing devices are also available. The EVBs work seamlessly with ClockBuilder Pro, enabling developers to quickly customize a device and evaluate performance.

http://www.silabs.com

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Intel ships Stratix 10 DX FPGAs to accelerate data centre workloads

Fri, Sep 20, 2019

FPGAs designed to support Intel Ultra Path Interconnect (UPI), PCI-Express (PCIe) Gen4 x16 and a new controller for Intel Optane technology are shipping from Intel. The Stratix 10 DX FPGAs are designed to boost acceleration of workloads in the cloud and enterprise when used with Intel’s data centre products.

The Stratix 10 DX FPGAs have new interfaces, including the option to support select Intel Optane DC persistent memory dual in-line memory modules (DIMMs). They increase bandwidth and provide coherent memory expansion and hardware acceleration for future Intel Xeon Scalable processors, reveals the company.

Data centre customers are using hardware accelerators, like FPGAs, for more computational speed from server systems running networking and cloud-based applications such as artificial intelligence (AI) training / inferencing or database-related workloads. The effective performance of hardware accelerators depends heavily on the communications bandwidth and latency between one or more server CPUs, available system memory and any attached accelerator, such as a graphics processor unit or application-specific standard products.

Diverting tasks to accelerators frees up CPU cores to become available to work on other higher priority workloads, increasing data centre operator efficiency, says Intel.

Stratix 10 DX FPGAs’ features include a memory controller which supports up to eight Intel Optane DC persistent memory modules per FPGA (up to 4Tbytes of non-volatile memory). There is also 100Gbyte per second Ethernet, HBM2 memory stacks and a quad-core Arm Cortex-A53 processor sub-system with peripherals.

The Stratix 10 DX joins the Stratix 10 GX, Stratix 10 SX SoC FPGAs, Stratix 10 TX and Stratix 10 MX FPGAs.

http://www.intel.com

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IP with 112G Ethernet PHY targets hyperscale data centre SoCs

HD LCD video controller has MIPI-CSI2 input for parking assist

Clock generators, buffers and PCIe clocks and buffers are AEC-Q100-qualified

Intel ships Stratix 10 DX FPGAs to accelerate data centre workloads

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