i.MX 93 applications processor enhances security at the edge, says NXP

Believed to be the industry’s first implementation of the Arm Ethos-U65 microNPU, the i.MX 93 applications processors are the first in NXP’s i.MX 9 series.

The applications processors are designed for automotive, smart home, smart building and smart factory applications, which use edge machine learning to anticipate user needs. They combine the Arm Ethos-U65 microNPU with a high level of security and integration to deliver efficient, fast, secure machine learning at the edge, for example in voice-assisted smart home and building systems. They can also be used in low power industrial gateways and automotive driver monitoring systems. 

The i.MX 93 family has a heterogenous multi-core architecture, including up to two 1.7GHz Arm Cortex-A55 applications processors and a real-time Cortex-M33 microcontroller subsystem with access to all SoC peripherals, including the 256 MACs / cycles Arm Ethos-U65 microNPU. This architecture delivers power-efficient machine learning across a variety of applications, including compact, battery-powered IoT devices, says NXP. 

The i.MX 93 family supports a variety of industrial and automotive connectivity interface protocols, in addition to broad multi-media interfaces. This also reduces the need for external hardware components and additional design work, to reduce the time to market as well as overall systems costs. 

Ron Martino, executive vice president and general manager, ege processing for NXP Semiconductors, believes: “The highly integrated i.MX 93 applications processors will help open an entirely new range of use cases at the edge, where you need to have that close tie-in to the sensor data to make fast decisions. This will enable a new generation of secured, efficient, intelligent devices across IoT, industrial IoT and automotive applications.”

NXP’s EdgeLock secure enclave is a standard on-die feature across the i.MX 9 series. It is a pre-configured, self-managed and autonomous security subsystem. It is particularly useful for developers without deep security expertise.

“We’re making it easier for developers to create, connect, and maintain innovative IoT devices by providing a comprehensive platform actively supported by the scale and expertise of Microsoft software, cloud and security experts,” said Halina McMaster, partner group program manager, Microsoft Azure Sphere. “Together with NXP, we are delivering a variety of Microsoft Azure Sphere-certified edge processors that provide a secured environment for customer applications, critical over-the-air update infrastructure, and more than 10 years of ongoing security improvements for every Azure Sphere chip,” she said. 

i.MX 93-CS processors with Azure Sphere are built with Microsoft Pluton enabled on the EdgeLock secure enclave. Pluton on EdgeLock secure enclave is the dependable hardware root of trust which is built into the silicon and enables the Azure Sphere security stack.

Machine learning application development on the i.MX 93 family will be enabled by the eIQ software development environment, including the eIQ Toolkit workflow tools, the GUI-based eIQ Portal development environment and eIQ inference engine options that will include the Arm Ethos-U65 microNPU as an inference target. 

The i.MX 93 applications processors implement NXP’s innovative Energy Flex architecture, enabling developers to optimize energy usage for each operating mode to create portable devices with longer battery life. 

http://www.nxp.com

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Bluefield-3 DPU accelerates virtual clouds, says Nvidia

With 400Gb/s Ethernet or NDR 400Gbits per second InfiniBand network connectivity, BlueField-3 DPU (data processing unit) offloads, accelerates, and isolates software-defined networking, storage, security, and management functions to improve data centre performance, efficiency and security, says Nvidia. 

The third-generation Bluefield infrastructure on a chip enables organisations to build software-defined, hardware-accelerated IT infrastructures from cloud to core data centre to edge, says the company. In addition to powerful computing and a range of programmable acceleration engines in the I/O path, BlueField-3 is addresses the infrastructure needs of the most demanding applications and software backwards compatibility through the Nvidia DOCA software framework. 

BlueField-3 DPUs transform traditional computing environments into secure and accelerated virtual private clouds, allowing organisations to run application workloads in secure, multi-tenant environments. It decouples data centre infrastructure from business applications and is claimed to deliver optimal bare-metal performance and native support for multi-node tenant isolation. 

BlueField-3 DPU features video streaming Storage NVMe over Fabrics (NVMe-oF), NVMe/ TCP, hyper converged infrastructure (HCI), encryption, data integrity, data de-duplication, decompression, erasure coding/RAID Security Distributed firewall, IDS/ IPS, root of trust and microsegmentation.

The portfolio includes one, two or four ports with up to 400Gbits per second connectivity, 16Gbyte on-board DDR5 memory. There is also a 1GbE out-of-band management port,  single port InfiniBand or dual ports of NDR200 / HDR (200Gbits per second), 32 lanes of PCIe Gen 5.0 and non-transparent bridging.

The ample memory consists of up to 16 Armv8.2+ A78 Hercules cores (64-bit), 8Mbyte L2 cache and 16Mbyte LLC system cache. There is also a programmable datapath accelerator, DDR DIMM support, including dual DDR5 5600Mtransfers per second DRAM controllers and ECC protection. 

For security, there is secure boot with public key accelerator (PKA) root-of-trust, secure firmware update and Flash encryption, MACsec / IPsec / TLS data-in-motion encryption, an AES-GCM 128 / 256-bit key, AES-XTS 256 / 512-bit data-at-rest encryption, connection tracking for stateful firewall and true random number generator (TRNG) storage.

 https://www.nvidia.com/

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NFC Type 2 tag IC has permanent write locks and configurable kill mode

Consumer engagement, production information and brand protection are offered with the ST25TN512 and ST25TN01K NFC Forum Type 2 tag ICs by STMicroelectronics. They can also be used for access control.

The ST25TN512 and ST25TN01K NFC tag ICs support multiple user-protection and privacy mechanisms including a 7-bit unique chip-identifier code, TruST25 digital signature, NFC Forum T2T permanent write locks at block level, and a configurable kill mode that permanently deactivates the tag.

The two ICs are certified to NFC Forum Type 2 specifications and leverage ISO 14443 standards. They can be used with NFC-compatible mobiles or a dedicated short-range reader. The embedded device memory includes up to 208 bytes (1664 bits) dedicated to user content.

There is also support for messages in NFC data exchange format (NDEF) which triggers native actions on a smartphone without needing a dedicated app, such as launching a web browser or starting Bluetooth pairing. Augmented NDEF (ANDEF) enables reading dynamic information such as custom messages and unique tap codes without explicitly updating the EEPROM.

The ST25TN512 and ST25TN01K are produced by a new in-house manufacturing process. Both NFC tag ICs contain an internal tuning capacitance of 50pF, which allows plug-and-play integration by inlay manufacturers. The tags harvest energy from the 13.56MHz RF transmitter field and require only an antenna to complete the design.

They also have a long data retention and operate over a wide temperature range of -40 to +85 degrees C. The ICs can be supplied in sawn and bumped wafer format or housed in a DFN5 package.

Both the ST25TN512 and ST25TN01K are available in volume production.

http://www.st.com

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Cross-domain automotive control microcontrollers enhance ECU integration

Microcontrollers designed to address the growing need to integrate multiple applications into a single chip and unify the electronic control unit (ECU) in vehicles, make up the RH850/U2B series.

Renesas says the cross-domain microcontrollers are built for the rigorous workloads required by vehicle motion in hybrid ICE and xEV traction inverter, high-end zone control, connected gateway and domain control applications. 

They join the company’s RH850/U2A microcontrollers for body and chassis control systems. Customers can also combine the microcontrollers with Renesas’ R-Car S4 SoC devices for automotive central gateway systems for scalable electronic / electrical architectures that are deemed the architectures for future vehicle generations. 

Naoki Yoshida, vice president, automotive digital products marketing division at Renesas, said: “The RH850/U2B microcontrollers . . . performance, memory integration and hardware-based support for new zone- and domain-control applications, particularly for powertrain and HEV/EV, while maintaining the stringent cost, safety, and security parameters required for these automotive systems”.

Designed for zone and domain applications, the 28nm RH850/U2B microcontrollers build on key functions from Renesas’ RH850/E2x series for powertrain and RH850/C1M-Ax series for HEV/EV motor control. At the same time they add enhancements including an accelerator IP, higher performance levels and increased security. This feature set enables users to integrate multiple ECU functions into a single ECU while adhering to stringent automotive-grade safety, security and real-time operation requirements.

The integrated hypervisor hardware-based virtualisation assist function allows multiple software systems with up to ISO26262 ASIL D functional safety levels to operate independently, without interference. It also reduces the virtualisation overhead to maintain real-time execution. Quality-of-service (QoS) provides a latency monitor and regulation function for all bus masters to ensure minimum bandwidth is always available. The RH850/U2B microcontrollers support safe and rapid full no-wait over the air (OTA) software updates with dual-bank embedded flash that allows the ECU to update and save images while the microcontrollers are in active mode and enables the ECU to operate from the original code if a failure occurs. Integrated motor control accelerator IP (EMU3S) works in conjunction with multiple dedicated motor control timer structures like GTM v4.1 and TSG3 to reduce CPU processing loads while achieving high-speed rotation. Dedicated data flow processor (DFP) accelerator IP enables the CPU to offload compute-heavy operations for complex control. 

The microcontrollers have up to eight 400MHz performance cores with four of them in lockstep architecture, with built-in flash targeting ASIL-D and ASIL-B applications. Integrated security functions support the Evita Full standard, including elliptic curve cryptography. There are multiple instances of AES128 lock-step modules for conflict-free, deterministic safe and secure communication.

The dedicated resolver / digital converter accelerator IP (RDC3X) processes analogue signals from a motor rotational angle sensor (resolver) or an inductive position sensor. 

The DR1000C is a RISC-V-based parallel co-processor IP with vector extension (DFP), licensed from NSITEXE, which supports the fast execution of complex mathematical algorithms.

Communication interfaces include Gigabit Ethernet TSN with switch support. 

The RH850/U2B microcontrollers will be sampling from April 2022. 

http://www.renesas.com

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