Xilinx says Alveo U55C is its most powerful accelerator card 

Purpose-built for high performance computing (HPC) and big data workloads, the Aleveo U55C was unveiled by Xilinx at SC21. 

The data centre accelerator card was launched alongside a new standards-based, API-driven clustering for deploying FPGAs at massive scale. 

The Alveo U55C accelerator is the company’s most powerful Alveo accelerator card to date and offers the highest compute density and HBM capacity in the Alveo accelerator portfolio. Used with Xilinx RoCE v2-based clustering, customers with large-scale compute workloads can now implement powerful FPGA-based HPC clustering using an existing data centre infrastructure and network, says Xilinx. 

“Scaling out Alveo compute capabilities to target HPC workloads is now easier, more efficient and more powerful than ever,” said Salil Raje, executive vice president and general manager, Data Center Group at Xilinx. “Architecturally, FPGA-based accelerators like Alveo cards provide the highest performance at the lowest cost for many compute-intensive workloads. By introducing a standards-based methodology that enables the creation of Alveo HPC clusters using a customer’s existing infrastructure and network, we’re delivering those key advantages at massive scale to any data centre,” he said.  

The Alveo U55C card delivers more parallelism of data pipelines, superior memory management, optimised data movement throughout the pipeline, and the highest performance-per-watt in the Alveo portfolio. 

The single-slot full height, half length (FHHL) form factor card has a low 150W (max) power. It doubles the HBM2 to 16Gbyte compared to its predecessor, the dual-slot Alveo U280 card. The U55C therefore provides more compute in a smaller form factor to create dense Alveo accelerator-based clusters. Target applications are high-density streaming data, high I/O math and big compute tasks like big data analytics and AI applications.

Leveraging RoCE v2 and data centre bridging, coupled with 200Gbits per second bandwidth, the API-driven clustering enables an Alveo network that competes with InfiniBand networks in performance and latency, with no vendor lock-in, says Xilinx. MPI integration allows for HPC developers to scale out Alveo data pipelining from the Vitis unified software platform. Using existing open standards and frameworks, it is now possible to scale out across hundreds of Alveo cards regardless of the server platforms and network infrastructure and with shared workloads and memory, Xilinx advises.

Software developers and data scientists can unlock the benefits of Alveo and adaptive computing through high-level programmability of both the application and cluster using the Vitis platform​. Vitis supports AI frameworks, like Pytorch and Tensorflow as well as high-level programming languages like C, C++ and Python, allowing developers to build domain solutions using specific APIs and libraries. Alternatively Xilinx software development kits can be used to accelerate targeted HPC workloads within an existing data centre. 

The Alveo U55C card is currently available via the company’s website and through authorised distributors. It is also available for evaluation via public cloud-based FPGA-as-a-service providers, as well as select co-location data centres for private previews. Clustering is available now for private previews, with general availability expected in Q2 2022. 

http://www.xilinx.com

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5G beamformer IC family includes dual-polarisation mmWave devices

Third-generation beamformer ICs by Renesas Electronics include two dual-polarisation mmWave devices optimized for 2×2 antenna architecture for 5G and broadband wireless applications. They are claimed to have best-in-class performance at n257, n258, and 261 bands. The integrated F5288 and F5268 transmitter / receiver (8T8R) chipsets are in a 5.1 x 5.1mm BGA package and are claimed to have the industry’s highest Tx output power capability in silicon, delivering more than 15.5dBm linear output power per channel. They are intended for cost-efficient radio design with extended signal reach for wireless infrastructure applications including wide area, small cell and macro basestations, as well as CPE (customer premises equipment) and fixed wireless access (FWA) access points. Communications customers can reduce design times by repurposing antenna array designs across different applications, advises Renesas. 

The F5288 and F5268 ICs feature a Dynamic Array Power (DAP) technology that enables high-efficiency operation at linear output power levels programmable from 10 to 16dBm. 

“Adequate signal range – or lack thereof – remains the biggest challenge as the industry shifts to 5G mmWave technologies for both urban and suburban mobile and fixed wireless networks,” said Naveen Yanduru, vice president of RF communications product division at Renesas.

The third-generation mmWave beamformer ICs’ dual-polarisation eight-channel architecture provides a symmetric and low loss antenna routing network to improve overall antenna efficiency, says Renesas. The exposed die package allows for efficient thermal management at the board with improved heat dissipation through the back of the IC. According to Renesas, temperature compensation techniques minimise RF performance degradation with varying temperatures The package pinmap is designed to simplify board design and reduce design risks. 

In addition to Dynamic Array Power technology for scaling output power, the F5288 and F5268 ICs feature ArraySense technology which allows users to monitor IC performance in array operation and apply critical corrections real-time. They also include RapidBeam advanced digital control technology to enable simultaneous synchronous and asynchronous control of several beamformer ICs to achieve extremely fast beamsteering operations. 

The F5288 operates at 26.5 to 29.5GHz and the F5268 operates at 24.25 to 27.5GHz. They also have phase and gain control which includes 360 degree phase control with true six-bit resolution and up to 31.5dB gain control in 0.5dB steps. There are improved Rx linearity modes and Rx noise figures as low as ~4.5dB at room temperature and under 5.5dB at temperatures up to 95 degrees C.

The F5288 and F5268 beamformer ICs and evaluation systems are available now. 

http://www.renesas.com 

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Multi-cell battery ICs tackle large, HV battery packs

Battery packs that packs that power e-scooters, energy storage, high-voltage power tools, and other high-voltage equipment can be managed with RAA48920x ICs. Renesas Electronics claims that the multi-cell battery front end ICs for battery management systems (BMS) accelerate battery development for mobility, uninterrupted power supplies (UPS) and energy storage systems. 

The ICs provide fast, flexible, cell balancing up to 200mA to enable fast recharging and high utilisation in large battery packs with hot plug tolerance up to 62V. 

BMS, or the ‘brains’ of the battery pack, is increasingly adopted in UPS and data centres, driving demand for ICs that can support higher voltage and larger cell battery pack sizes, said Andrew Cowell, vice president at Renesas’, mobility, infrastructure and IoT power business division. The RAA489206 and RAA489204 ICs have been designed to simplify the design process and create robust, cost-effective battery systems for the growing mobility, UPS back up and energy storage markets, he explained.

The RAA489206 is designed for higher voltage mobility applications where larger cell count and temperature variance across cells are more likely to lead to cell-to-cell imbalances. It provides full high-side battery protection and monitoring for 4S to 16S cell battery packs. The RAA489204 provides improved daisy chain operation with accelerated device-to-device communication and enhanced diagnostics compared with previous-generation devices. It also has internal cell balancing options and support for the higher voltages and cell count required by UPS systems, grid back up and other energy storage systems.  

The ICs’ high integration simplifies the design cycle and reduces customers’ system bill of materials’ costs “significantly”, claims Renesas, adding that it also accelerates design and bill of material selection time from months to weeks. 

The ICs also feature extensive built-in self diagnostics, improving safety functionality, reducing firmware workload and easing the design burden for meeting safety standards. They are pin-to-pin compatible with Renesas’ previous battery front end devices.

Both the RAA489206 and RAA489204 ICs are available now. 

http://www.renesas.com

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Lattice extends sensAI software stack to add AI / ML to edge applications

Features for power-efficient AI / ML (artificial intelligence / machine learning) inferencing are incorporated into the Lattice sensAI stack have been announced by Lattice Semiconductor.

The latest version (v4.1) of the sensAI solution stack is available now and supports Lattice’s roadmap of AI-based applications. Enhancements and new features include user presence detection to automatically power on/off client devices as a user approaches or departs, attention tracking to lower a device’s screen brightness to conserve battery life when the user isn’t looking at the screen, face framing to improve the video experience in video conferencing applications and onlooker detection to realise when someone is standing behind a device; it blurs the screen to maintain data privacy.

There is also expanded application support, with improved performance and accuracy for object and defect detection applications in automated industrial systems. There is also a new hardware platform for voice and vision-based ML application development featuring an onboard image sensor, two I2S microphones, and expansion connectors for adding additional sensors.

An updated neural network compiler supports Lattice sensAI Studio, a GUI-based tool with a library of AI models that can be configured and trained for popular use cases. sensAI Studio now supports AutoML features to enable creation of ML modules based on application and dataset targets. Several of the models based on the Mobilenet ML inferencing training platform are optimised for the latest Nexus FPGA family, Lattice CertusPro-NX. The stack is compatible with other ML platforms, including the latest versions of Caffe, Keras, TensorFlow, and TensorFlow Lite.

To meet the demand for more responsive and context-aware user experiences, high quality video conferencing, and collaboration applications on client compute devices, Lattice Nexus FPGAs and the sensAI stack can be used to develop computer vision and sensor fusion applications that improve engagement, privacy, and collaboration for users. For example, a client device can leverage image data from its camera to determine if someone is standing too close behind the user and blur the screen for privacy or lengthen battery life by dimming the device’s display when it ‘sees’ the user’s attention is focused elsewhere.

“AI applications based on vision, sound, and other sensors will revolutionise the client computing experience,” believes Matt Dobrodziej, vice president of segment marketing and business development at Lattice. The sensAI solution stack supports a roadmap of edge AI applications that make client devices contextually aware of how, when and where they’re being used, he explains. The Nexus FPGAs deliver that functionality with low power consumption, he adds.

Compute devices using an AI application developed with the sensAI solution stack and running on a Lattice FPGA have a 28 per cent longer battery life in comparison to devices powering AI applications with their CPUs, Lattice reports. The sensAI solution stack also supports in field software updates to keep pace with AI algorithms and provides OEMs the flexibility to choose from different sensor and SoC technologies.

Lattice is working with AI ecosystem partner, such as Mirametrix, to develop the Lattice client compute AI experience roadmap. Its Glance attention-sensing software captures a user’s face, eyes, and gaze to understand user awareness and attention. The technology is used to create smart devices capable of more natural and immersive user experiences and device interaction, said Stephen Morganstein, Mirametrix’s vice president. “Lattice’s sensAI solution stack and low power FPGAs help developers implement novel AI capabilities that can improve a device’s battery life,” he said.

http://www.latticesemi.com

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