Latest News

Microchip claims to have developed the industry’s first Tbit-scale Ethernet PHY that enables the highest-density 400GbE and FlexE connectivity.

The META-DX1 family of Ethernet physical layer (PHY) devices enables telecomms service providers to build networks using routing and switching to reduce cost, optimise bandwidth and increase capacity. The META-DX1 also integrates the Media Access Control Security (MACsec) security engine.

The device, developed by Microchip’s subsidiary, Microsemi, combines Ethernet ports from 1Gigabit Ethernet (GbE) to 400GbE, Flexible Ethernet (FlexE), Media Access Control Security (MACsec) link encryption and nanosecond timestamping accuracy. Its Tbit capacity is designed to address the industry transition from 100GbE to 400 GbE to support traffic within hyperscale data centres. This traffic volume is expected to quadruple by 2021 (source: Cisco’s Global Cloud Index), with data centre-to-data centre traffic growing at more than a 30 per cent cumulative annual growth rate (CAGR).

The META-DX1 enables line cards to quadruple in capacity, from 3.6Tbits per second to 14.4Tbits per second with 36 ports of 400GbE or 144 ports of 100GbE.

The MACsec engine secures traffic leaving the data centre or enterprise premises. FlexE enables both cloud and telecomms service providers to reduce capex by optimally configuring links beyond today’s fixed-rate Ethernet so they can use low-cost, high-volume optics, while meeting the increasing capacity requirements. Combining the MACsec and FlexE in one device, meets the next phase of capacity scaling in data centre interconnect (DCI) buildouts, adds Microchip.

The META-DX1 is further differentiated in the market with the addition of integrated flexible crosspoint switching, which makes it easier for OEMs to navigate the market transition from 25Gbits per second psnon return to zero (NRZ) and 56Gbits per second pulse amplitude modulation (PAM) -based architectures by enabling them to support a single design or device for both 100GbE (QSFP28) and 400GbE (QSFP-DD) optics. Timestamping is also provided with nanosecond-level accuracy on every port to ensure network builds will meet the challenging timing requirements of 5G mobile basestation deployments.

Initial META-DX1 family members will sample during Q3 2019. All devices are hardware-compatible and supported by the same software developer’s kit.

http://www.microchip.com

Industrial computing developers can integrate the eSPI standard in existing equipment, using the ECE1200 bridge from Microchip. According to the company, it minimises development costs and extends product lifecycles.

The eSPI bus technology supports new computing with next-generation chipsets and CPUs.

It is believed to be the industry’s first commercially available eSPI-to-low pin count (LPC) bridge. The ECE1200 bridge allows developers to implement the eSPI standard in boards with legacy LPC connectors and peripherals, says Microchip. This allows the developers to implement the eSPI standard while preserving significant investments in legacy LPC equipment and substantially minimising development costs and risk.

The eSPI-to-LPC bridge allows developers to maintain long lifecycles while supporting the eSPI bus technology that is required for new computing applications using the next generation of chipsets and CPUs. To reduce risk for developers, the eSPI bus technology has been through intensive validation for industrial computing applications and has been validated with leading processor companies.

The ECE1200 detects and supports modern standby mode with low standby current. This helps industrial computing developers to manage operating costs and efficiencies. The does not require any software.

To streamline development, the ECE1200 comes with a BIOS porting guide, schematics and a layout guide.

The ECE1200-I/LD is available today in a 40-pin VQFN package.

http://www.microchip.com