Design flows are based on the Integrity 3D-IC platform
Design flows based on the Integrity 3D-IC platform have been announced by Cadence Design Systems to support the TSMC 3Dblox standard for 3D front end design partitioning in complex systems.
Cadence flows are optimised for all of TSMC’s latest 3DFabric offerings, including integrated fan-out (InFO), Chip-on-Wafer-on-Substrate (CoWoS) and System-on-Integrated-Chips (TSMC-SoIC) technologies. By using these design flows, customers can accelerate the development of advanced multi-die package designs for emerging 5G, AI, mobile, hyperscale computing and IoT applications, said Cadence.
The Cadence Integrity 3D-IC platform combines system planning, packaging, and system level analysis and is certified for use with the TSMC 3DFabric and the 3Dblox 1.5 specification. The flows based on this platform incorporate new features like 3D routability-driven bump assignment and hierarchical bump resource planning. 3Dblox, which is inherently supported by the Integrity 3D-IC platform, provides a seamless interface for Cadence system analysis tools for early power delivery network (PDN) and thermal analysis via the Cadence Voltus IC Power Integrity Solution and Celsius Thermal Solver system analysis tools; extraction and static timing analysis via the Cadence Quantus Extraction Solution and Tempus Timing Signoff and system level layout versus schematic (LVS) checks via the Cadence Pegasus Verification system.
“3D-IC technology is key to meeting the performance, physical size, and power consumption requirements to enable next-generation HPC and mobile applications,” said Dan Kochpatcharin, head of the design infrastructure management division at TSMC. “By continuing our collaboration with Cadence, we’re enabling customers to leverage our comprehensive 3DFabric technologies and the Cadence flows that support our 3Dblox standard, so they can significantly improve 3D-IC design productivity and speed time to market,” he added.
“The Cadence flows based on the Integrity 3D-IC platform incorporate everything a customer needs to quickly design a leading-edge 3D-IC using TSMC’s latest 3DFabric technologies,” added Dr. Chin-Chi Teng, senior vice president and general manager in the digital and signoff group at Cadence.
The Cadence Integrity 3D-IC platform, including Allegro X packaging technologies, is part of the company’s broader 3D-IC offering and aligns with the Cadence Intelligent System Design™ strategy, enabling SoC design excellence. The Cadence reference flows and tutorials are available on TSMC Online now.
