CrossLinkPlus FPGAs speed and enhance video bridging
Lattice Semiconductor has introduced the CrossLinkPlus FPGA family for MIPI D-PHY based embedded vision systems. The new devices are low power FPGAs featuring integrated flash memory, a hardened MIPI D-PHY and high-speed I/Os for instant-on panel display performance, and flexible on-device programming capabilities.
Developers want to enhance the user experience by adding multiple image sensors and/or displays to embedded vision systems, while also meeting system cost and power budgets.
Key features of the CrossLinkPlus family of FPGAs include on-device reprogrammable flash memory to enable instant-on (< 10 ms), hardened, pre-verified MIPI D-PHY interface supporting speeds up to 6 Gbps per port and broad support for high-speed I/O interfaces such as LVDS, SLVS and subLVDS.
Power consumption can be as low as 300 microwatt (standby) or 5 microwatt (operating).
Lattice also provides ready-to-use IPs and reference designs to accelerate implementation of enhanced sensor and display bridging, aggregation, and splitting functionality, a common requirement for industrial, automotive, computing, and consumer applications. There is a comprehensive IP library, including MIPI CSI-2, MIPI DSI, OpenLDI transmitters and receivers. These IPs are compatible with other Lattice FPGAs for easy design portability.
This new series is fully compatible with the Lattice Diamond design software tool flow, from synthesis and design capture through implementation, verification, and programming.
CrossLinkPlus uses its on-chip flash to support instant-on (minimising visual artifacts that detract from the user experience) and flexible device reprogramming in the field.
“The use of MIPI D-PHY in applications ranging from industrial control equipment displays to AI security cameras is booming as OEMs look to capitalize on the economies of scale driven by the MIPI ecosystem,” said Peiju Chiang, product marketing manager, Lattice Semiconductor.
“Lattice’s new CrossLinkPlus FPGAs combine the flexible programmability and speedy parallel processing of FPGAs with vision-specific hardware, software, pre-verified IPs and reference designs. This lets OEMs devote more time to building innovative applications and less time enabling standard functions that don’t offer any competitive differentiation.”
