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Qualcomm launches next-generation XR and AR platforms

Wed, Oct 04, 2023

Two spatial computing platforms called Snapdragon XR2 Gen 2 and Snapdragon AR1 Gen 1 have been introduced by Qualcomm to enable the next generation of mixed reality (MR), virtual reality (VR) devices and smart glasses.

Snapdragon XR2 Gen 2 brings premium MR and VR technology into a single chip architecture for immersive experiences in thinner and more comfortable headsets, that do not require an external battery pack.

It is engineered to deliver a lag-free experience with immersive sound blending virtual content with the user’s physical surroundings and transition seamlessly between MR and VR experiences.

Snapdragon AR1 Gen 1 platform is designed with power optimisations for sleek, lightweight smart glasses that enable the user to capture, share or live-stream hands-free, directly from the glasses. On-device AI enables personal assistant experiences such as audio quality enhancement, visual search and real-time translation. There is also support for a visual heads-up display to enable content consumption, including video, that blend seamlessly in the users’ field of view.

The platforms were developed in close collaboration with Meta and will commercially debut on Meta devices in 2023. The Meta Quest 3 will be powered by Snapdragon XR2 Gen 2 Platform, and Ray-Ban Meta smart glasses collection will be powered by Snapdragon AR1 Platform. Other manufacturers are expected to follow next year.

“At Meta, we’re focused on developing the technologies of the future in mixed reality and smart glasses, as well as the foundational innovations that will one day power our vision for AR glasses,” said Andrew “Boz” Bosworth, Meta’s CTO and Head of Reality Labs.

“The Snapdragon XR2 Gen 2 and Snapdragon AR1 platforms are the latest purpose-built processors that are designed to power the next generation of MR and VR devices and sleek smart glasses for all,” said Hugo Swart, vice president and GM of XR, Qualcomm Technologies. “The commercial debut of these two platforms with Meta is a further step forward in realizing our joint vision – unlocking premium, all-in-one XR devices and smart glasses that are affordable to users around the globe.”

http://www.qualcomm.com

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IP and SDK accelerate on-device and edge AI design, says Cadence

Fri, Sep 15, 2023

AI IP and software tools to address the escalating demand for on-device and edge AI processing have been unveiled by Cadence. The scalable Cadence Neo neural processing units (NPUs) deliver a range of AI performance in a low-energy footprint, said the company and this is claimed to bring new levels of performance and efficiency to AI SoCs.
The Neo NPUs deliver up to 80TOPS performance in a single core, in order to support both classic and new generative AI models. They can also offload AI/ML execution from any host processor, including application processors, general-purpose microcontrollers and DSPs. This is achieved with a simple and scalable AMBA AXI interconnect.
Cadence has also introduced the NeuroWeave software development kit (SDK) which it said provides developers with a “one-tool” AI software solution across Cadence AI and Tensilica IP products for no-code AI development.
“While most of the recent attention on AI has been cloud-focused, there are an incredible range of new possibilities that both classic and generative AI can enable on the edge and within devices,” pointed out Bob O’Donnell, president and chief analyst at TECHnalysis Research. For these intuitive, intelligent devices to be realised will need a flexible, scalable combination of hardware and software solutions with a range of power requirements and compute performance, “all while leveraging familiar tools” he believed. “New chip architectures that are optimised to accelerate ML models and software tools with seamless links to popular AI development frameworks are going to be incredibly important parts of this process,” he added.
The Neo NPUs are suitable for power-sensitive devices as well as high-performance systems with a configurable architecture. SoC architects will be able to integrate an optimal AI inferencing solution in a range of products, including intelligent sensors, IoT and mobile devices, cameras, hearables/wearables, PCs, AR/VR headsets and advanced driver-assistance systems (ADAS). New hardware and performance enhancements and key features/capabilities include:
The single core NPUs are scalable from 8GOPS to 80TOPS, with further extension to hundreds of TOPS with multi-core devices, said Cadence. They support 256 to 32K MACs per cycle, allowing SoC architects to optimise embedded AI to meet power, performance and area (PPA) tradeoffs.
Offloading of inferencing tasks from any host processor (e.g., DSPs, general-purpose microcontrollers or application processors) significantly improves system performance and power, said Cadence.
Support for Int4, Int8, Int16 and FP16 data types across a wide set of operations that form the basis of CNN, RNN and transformer-based networks allows flexibility in neural network performance and accuracy tradeoffs while the NPUs offer up to 20 times higher performance than the first-generation Cadence AI IP, with two to five time the inferences per second per area (IPS/mm2) and five to 10 times the inferences per second per Watt (IPS/W)

Upgrades to the common software toolchain include the NeuroWeave software development kit (SDK). Providing customers with a uniform, scalable and configurable software stack across Tensilica DSPs, controllers and Neo NPUs to address all target applications, the NeuroWeave SDK streamlines product development and enables an easy migration as design requirements evolve. It supports many industry-standard domain-specific ML frameworks, including TensorFlow, ONNX, PyTorch, Caffe2, TensorFlow Lite, MXNet and JAX for automated end-to-end code generation, together with Android Neural Network Compiler; TF Lite Delegates for real-time execution and TensorFlow Lite Micro for microcontroller-class devices.
The Neo NPUs and the NeuroWeave SDK are expected to be in general availability beginning in December 2023.

http://www.cadence.com

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MRigidCSP package is claimed to increase MOSFET’s mechanical strength

Mon, Sep 04, 2023

Robust package technology, MRigidCSP, by Alpha and Omega Semiconductor (AOS), is initially offered on its AOCR33105E, 12V, common drain, dual N-channel MOSFET. The packaging technology is designed to decrease on resistance while increasing mechanical strength, and is particularly suited to battery applications in smartphones, tablets and ultra-thin notebooks.
AOS explained that fast charging, which requires lower power loss in the battery management circuit, is now widely adopted for portable devices. As the charging currents increase, ultra-low electrical resistance is needed for improved performance. In standard wafer-level chip scale packages (WL-CSPs), the substrate can be a significant portion of the total resistance when back-to-back MOSFETs are employed in battery management applications. A thinner substrate reduces the overall resistance but drastically reduces the package’s mechanical strength. This reduction of mechanical strength can lead to more stress during the PCB assembly reflow process, potentially causing warping or cracking in the die and, ultimately, failure in the application. The AOCR33105E is designed with trench-power MOSFET technology in a common drain configuration for design simplicity. It features low on resistance with ESD protection to improve performance and safety in battery management, such as protection switches and mobile battery charging and discharging circuits.
“Incorporating the AOS MRigidCSP packaging technology with our new dual N-channel MOSFET combines electrical performance improvements with the benefit of high robustness,” said Peter H. Wilson, senior MOSFET product line marketing director at AOS.
AOS designed the MRigidCSP package technology to be used with high aspect ratio CSP die sizes. The CSP construction delivers “a significantly strengthened battery MOSFET that won’t warp or break during the board manufacturing process,” added Wilson.
The AOCR33105E is available in a 2.08 x 1.45mm package, with RDS(on) of 3mOhm at 4.5V / 4.2mOhm at 3.1V.
The AOCR33105E in the MRigidCSP package is immediately available in production quantities with a lead time of 14 to 16 weeks. It is RoHS 2.0 compliant and is halogen-free.

http://www.aosmd.com

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Embedded chip antennas are small and durable for the IoT

Tue, Aug 08, 2023

Surface mounted embedded antennas have been added to the antenna portfolio by Amphenol RF. The surface mounted chip antennas offer electrical performance up to 8.5GHz and support cellular 4G/5G-FR1 frequencies as well as Wi-Fi and Bluetooth / Bluetooth Low Energy (BLE) and LoRa, UWB and GNSS.

The embedded RF antennas are compact and have a durable construction, making them suitable for IoT and smart devices.

By surface mounting the chip antenna directly on the PCB, with antenna ensure there is no need for external antennas. They are manufactured from ceramic or FR-4 materials and are omnidirectional. In addition, said Amphenol RF, they are easy to tune and available in tape and reel packaging.

The small size of ceramic chip antennas enables efficient integration into compact devices where space is at a premium. These antennas are well suited for smart utility meters, robotics, intelligent transport systems, set-top boxes and gateways, and mobile electronic wallets.

Amphenol RF provides local technical support and matching of antennas.

Amphenol RF manufactures coaxial connectors for use in radio frequency, microwave, and data transmission system applications. Headquartered in Danbury, Connecticut, USA, Amphenol RF has sales, marketing and manufacturing locations in North America, Asia and Europe. Standard products include RF connectors, coaxial adapters and RF cable assemblies. Custom engineered products include multi-port ganged interconnect, blind mate and hybrid mixed-signal solutions.

https://www.amphenolrf.com

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Qualcomm launches next-generation XR and AR platforms

IP and SDK accelerate on-device and edge AI design, says Cadence

MRigidCSP package is claimed to increase MOSFET’s mechanical strength

Embedded chip antennas are small and durable for the IoT

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