Single power monitoring IC is industry-first, claims Microchip

Claimed to be the industry’s first two-channel device with native 16bit resolution, the PAC1932, and the three-channel PAC1933 are single power monitoring ICs by Microchip.

The power monitoring devices measure from 0 to 32V on a single chip, enabling designers to improve power measurement accuracy. The two-channel device is believed to be the industry’s first with native 16bit resolution, providing leading flexibility across a wide measurement range.   

The PAC1932/33 devices include what is needed to measure power on a single IC, integrating multiple channels in a single package for applications such as point of sale (PoS) systems, ATMs and building automation. This reduces costs for system designers, consolidates the bill of materials (BoM) as the measurement of sub-1.0 to 20V voltage rails normally require separate components to measure each rail efficiently, points out Microchip. The PAC1932/33 measure voltage rails up to 32V and also relieves developers from having to reconfigure measurement resolution between low and high current load events.

As the industry’s only two-channel device with 16-bit power measurement, the PAC1932 can measure without host intervention for 17 minutes, relieving developers from adjusting voltage or current range to measure power and energy. The devices include two 16bit analogue to digital converters (ADCs) that can measure voltage and current simultaneously, enabling developers to extract a true power measurement. According to Microchip, developers can design systems to efficiently save power.

As applications continue to seek ways to reduce power consumption, precision DC power measurement has grown as a key element for energy savings.  Microchip also offers a four-channel PAC1934 for improved power measurement for Windows 10 devices; the PAC1932/33 two and three channel power monitoring ICs offer improved power measurement for low voltage, high power applications in markets such as embedded computing and networking.

The PAC1932/33 work in conjunction with Linux and Windows 10 software drivers. The ADM00805 register-compatible evaluation board can be used to start development with a graphical user interface reporting Vsense, Vbus, power and accumulated power.

The two-channel PAC1932 and three-channel PAC1933 power monitoring ICs are available now for sampling and in volume production.

http://www.microchip.com/PAC1932

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Scalable digital controllers simplify power supply design, says Renesas Electronics

Two PMBus-compliant, digital DC/DC controllers released by Renesas Electronics, provide single output point of load (PoL) conversions for FPGAs, DSPs, ASICs, network processors and general purpose system rails. The ISL68300 has integrated MOSFET drivers while the ISL68301 has PWM output to simplify the design of power supplies for data centre, wired and wireless communications, and factory automation equipment.

The ISL68300 can drive discrete external MOSFETs directly, while the ISL68301 pairs with Renesas’ smart power stages or DrMOS power stages to create a complete voltage regulator solution.

The ISL68300 and ISL68301 digital controllers feature a high-speed current share bus that parallels up to eight controllers in an eight-phase 240A+ current share configuration. Both controllers implement Renesas’ digital ChargeMode control modulation, which responds to load transients in a single switching cycle, and provides an inherently stable control loop without requiring external compensation. This modulation architecture significantly reduces output capacitor requirements and minimises V out undershoot and overshoot, claims Renesas.

The scalability of the ISL68300 and ISL68301 single output digital controllers is claimed to provide industry leading performance and support a range of load currents.   

Engineers can use the PowerNavigator GUI with the ISL68300 and ISL68301 to simplify power supply set-up, sequencing, configuration and monitoring, including all device parameters and telemetry. Full schematic designs are completed in minutes, and the GUI with PMBus makes it easy to control the entire design and change features without soldering components or rework, adds Renesas.

The ISL68300 and ISL68301 digital controllers can parallel up to eight controllers in a single droop-less current sharing output. Output voltage range is 0.45 to 5.5V and input range is 4.75 to 16V or 4.5 to 5.5V.

The proprietary single-wire Digital-DC (DDC) serial bus enables voltage sequencing and fault spreading with other Renesas digital power ICs. Another feature is the cycle-by-cycle inductor peak current protection and configurable fault protection for Vout under-voltage, over-voltage, V in under-voltage/over-voltage and temperature. The non volatile memory stores operating parameters and records telemetry fault events.

In a typical FPGA power supply, the ISL68300 and ISL68301 digital controllers provide single output 10 to 40A+ for auxiliary rails, DDR memory, and system rails. The companion Renesas digital multiphase controllers use smart power stages to provide dual output 15 to 70A, or higher core power.

The ISL68300 is available now in a 4.0 x 4.0, 24-lead QFN package. The ISL68301 with PWM output for pairing with ISL99227B smart power stages or DrMOS power stages is available now in a 4.0 x 4.0mm, 24-lead QFN package.

Single-phase and two-phase evaluation boards are also available.

http://www.renesas.com

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DRAM transitions to 10nm for 5G and AI-powered mobile applications

Claimed to be the first 8Gbit LPDDR5 DRAM for 5G and AI-powered mobile applications, Samsung has unveiled its 10nm class memory. Samsung says that since bringing the first 8Gbit LPDDR4 to mass production in 2014, the company has been setting the stage to transition to the LPDDR5 standard for use in 5G and artificial intelligence (AI)-powered mobile applications.

The 8Gbit LPDDR5 has been added to Samsung’s premium DRAM lineup, which includes 10nm-class 16Gbit GDDR6 DRAM and 16Gbit DDR5 DRAM.

The 8Gbit LPDDR5 boasts a data rate of up to 6,400 Mbit per second, which is 1.5 times as fast as the mobile DRAM chips used in current flagship mobile devices (LPDDR4X, 4266 Mbits per second), says Samsung. With the increased transfer rate, the new LPDDR5 can send 51.2Gbytes of data, or approximately 14 full-HD video files (3.7Gbyte each), in a second.

The 10nm-class LPDDR5 DRAM will be available in two bandwidths – 6,400Mbits per second at a 1.1 operating voltage and 5,500Mbits per second at 1.05V. These options make the DRAM a versatile mobile memory for next-generation smartphones and automotive systems. To achieve this performance advance, Samsung doubled the number of memory ‘banks’ (sub divisions within a DRAM cell) from eight to 16. The LPDDR5 DRAM can attain a much higher speed while reducing power consumption, adds Samsung. The 8Gbit LPDDR5 also makes use of an advanced, speed-optimised circuit architecture that verifies and ensures the chip’s speed performance.

To maximise power savings, the 10nm-class LPDDR5 has been engineered to lower its voltage in accordance with the operating speed of the corresponding application processor, when in active mode. It also has been configured to avoid overwriting cells with ‘0’ values. There is also a ‘deep sleep mode’, which cuts the power usage to approximately half the ‘idle mode’ of the current LPDDR4X DRAM. As a result, the 8Gbit LPDDR5 DRAM will deliver power consumption reductions of up to 30 per cent, maximising mobile device performance and extending the battery life of smartphones.

Samsung says the LPDDR5 will be able to power AI and machine learning applications, and will be UHD-compatible for mobile devices worldwide.

Samsung, together with leading global chip vendors, has completed functional testing and validation of a prototype 8Gbyte LPDDR5 DRAM package, which is comprised of eight 8Gbit LPDDR5 chips.

http://www.samsung.com/semiconductor

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Wideband microwave synthesiser has VCO for ‘breakthrough’ performance

Claimed to deliver an industry leading phase noise, the ADF5620 is a wideband fractional-N synthesiser from Analog Devices.

It has an integrated voltage-controlled oscillator (VCO) and generates RF outputs from 55MHz to 15GHz and provides the industry’s lowest phase noise performance on a single chip, claims ADI.

The synthesiser is designed for markets as diverse as aerospace and defence, wireless infrastructure, microwave point-to-point links, electronic test and measurement, and satellite terminals.

When compared to alternative solutions that require multiple narrowband GaAs voltage controlled oscillators and phase-locked loops (PLLs), the ADF5610 offers 50 per cent less power dissipation, a smaller footprint and simpler architecture, says ADI, all of which translates into bill of materials cost savings and reduced time to market.

Developed on ADI’s proprietary SiGe BiCMOS process, the ADF5610 enables high modulation bandwidths and low BIT error rates. It features industry leading VCO phase noise (-114dBc/Hz at 100kHz offset and -165dBc/Hz at 100MHz offset both at 10GHz) and low normalised phase noise floor (FOM) of -229dBc/Hz. The integrated PLL function provides fast frequency hopping and lock times (less than 50 micro seconds with appropriate loop filter). The phase detector spurious levels are below -45dBc typical, and the RF output power level is 6dBm.

The ADF5610 wideband fractional-N synthesizer is supported by the ADIsimPLL, ADI’s PLL synthesiser design and simulation tool for assessing phase noise, lock time, jitter and other design considerations. It is also customer programmable through the use of integrated SPI and control software.

The ADF5610 is specified over the -40 to +85 degree C range. It operates from nominal 3.3V analogue and digital power supplies as well as 5V charge pump and VCO supplies, and features 1.8V logic-level compatibility. The synthesiser also contains hardware and software power down modes.

The ADF5610 is in production from next month and supplied in a 7.0 x 7.0mm LFCSP.

http://www.analog.com

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