Intel’s Integrated Photonics Solutions (IPS) Group has announced the industry’s most advanced and first-ever fully integrated optical compute interconnect (OCI) chiplet co-packaged with an Intel CPU and running live data. Intel’s OCI chiplet represents a leap forward in high-bandwidth interconnect by enabling co-packaged optical input/output (I/O) in emerging AI infrastructure for data centres and high performance computing (HPC) applications.
This first OCI chiplet is designed to support 64 channels of 32 gigabits per second (Gbps) data transmission in each direction on up to 100 meters of fibre optics and is expected to address AI infrastructure’s growing demands for higher bandwidth, lower power consumption and longer reach. It enables future scalability of CPU/GPU cluster connectivity and novel compute architectures, including coherent memory expansion and resource disaggregation.
AI-based applications are increasingly deployed globally, and recent developments in large language models (LLM) and generative AI are accelerating that trend. Larger and more efficient machine learning (ML) models will play a key role in addressing the emerging requirements of AI acceleration workloads. The need to scale future computing platforms for AI is driving exponential growth in I/O bandwidth and longer reach to support larger processing unit (CPU/GPU/IPU) clusters and architectures with more efficient resource utilisation, such as xPU disaggregation and memory pooling.
Electrical I/O supports high bandwidth density and low power, but only offers short reaches of about one meter or less. Pluggable optical transceiver modules used in data centres and early AI clusters can increase reach at cost and power levels that are not sustainable with the scaling requirements of AI workloads. A co-packaged xPU optical I/O solution can support higher bandwidths with improved power efficiency, low latency and longer reach – exactly what AI/ML infrastructure scaling requires.
The fully Integrated OCI chiplet leverages Intel’s silicon photonics technology and integrates a silicon photonics integrated circuit (PIC), which includes on-chip lasers and optical amplifiers, with an electrical IC. The OCI chiplet demonstrated at OFC was co-packaged with an Intel CPU but can also be integrated with next-generation CPUs, GPUs, IPUs and other system-on-chips (SoCs).
This first OCI implementation supports up to 4 terabits per second (Tbps) bidirectional data transfer, compatible with peripheral component interconnect express (PCIe) Gen5. The live optical link demonstration showcases a transmitter (Tx) and receiver (Rx) connection between two CPU platforms over a single-mode fibre (SMF) patch cord. The CPUs generated and measured the optical Bit Error Rate (BER), and the demo showcases the Tx optical spectrum with 8 wavelengths at 200 gigahertz (GHz) spacing on a single fibre, along with a 32 Gbps Tx eye diagram illustrating strong signal quality.
The current chiplet supports 64 channels of 32 Gbps data in each direction up to 100 meters (though practical applications may be limited to tens of meters due to time-of-flight latency), utilising eight fibre pairs, each carrying eight dense wavelength division multiplexing (DWDM) wavelengths. The co-packaged solution is also remarkably energy efficient, consuming only 5 pico-Joules (pJ) per bit compared to pluggable optical transceiver modules at about 15 pJ/bit. This level of hyper-efficiency is critical for data centres and high-performance computing environments and could help address AI’s unsustainable power requirements.
These PICs were packaged in pluggable transceiver modules, deployed in large data centre networks at major hyperscale cloud service providers for 100, 200, and 400 Gbps applications. Next generation, 200G/lane PICs to support emerging 800 Gbps and 1.6 Tbps applications are under development.
Intel is also implementing a new silicon photonics fab process node with state-of-the-art device performance, higher density, better coupling and vastly improved economics. Intel continues to make advancements in on-chip laser and semiconductor optical amplifier (SOA) performance, cost (greater than 40% die area reduction) and power (greater than 15% reduction).
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Advantech announces new CoM with Rockchip for embedded vision applications
Advantech has introduced the ROM-6881, a SMARC 2.1 computer-on-module featuring Rockchip’s RK3588 and RK3588J chipsets, featuring eight-core processors, with up to 6.0 TOPS of AI inference capability. The ROM-6881 also supports high-resolution video with 8K@30fps video encoding and 8K@60fps decoding, ensuring efficient, high-quality display and resolution. This module enhances edge IoT applications in autonomous mobile robots (AMRs), medical fields, surveillance, robotics, and beyond.
The ROM-6881 is powered by the Rockchip processor RK3588. It features a total of eight processing cores (4 x Arm Cortex-A76 and 4 x Arm Cortex-A55) that can reach speeds of up to 2.4GHz. All eight cores are built using an advanced 8nm process, providing a 300% increase in performance over the previous RK3399 processor. This ensures optimal computing power tailored for platform management and a diverse range of feature-rich applications. Specifically designed for Edge AI applications, the RK3588 integrates a 6-TOPs NPU accelerator, giving it impressive AI computing capabilities.
The ROM-6881 supports 8K@60fps H.265 and VP9 decoding, as well as 8K@30fps encoding capabilities. Its integrated 3D GPU ensures efficient, high-quality 3D rendering and display of panoramic content. Additionally, the ROM-6881 is equipped to handle four MIPI CSI cameras, two USB 3.0, and three USB 2.0 signals, enabling access to multiple cameras simultaneously. Moreover, the module features a rich array of display interfaces including HDMI, DP, LVDS/DSI, and eDP for up to four screens. The ROM-6881 is well-suited for medical equipment such as endoscopes, hemodialysis, and AI-based in vitro diagnostics (IVD) systems.
Industrial robots and Automated Guided Vehicles (AGVs) often demand solutions that provide high data throughput, low latency, minimal power consumption, and cost efficiency. The ROM-6881 features a variety of interfaces including two gigabit ports, two USB 3.0 ports, three USB 2.0 ports, SATA, and UARTs, making it simple to integrate peripherals such as LiDAR, motors, IMUs, and cameras to maximize AMR efficiency. Moreover, the ROM-6881’s four PCIe 3.0 slots provide flexible expansion, allowing for enhancements in wired networks and the addition of FPGA, Wi-Fi 6, and 5G modules.
The ROM-6881 supports multiple operating systems, including Debian and Android. To facilitate advanced edge AI development, users can leverage the RKNN Toolkit developed by Rockchip. This toolkit handles AI model conversions as well as inference and performance within an Ubuntu PC environment. For robotics applications, the ROM-6881 runs the Robot Operating System (ROS2), providing a flexible framework for development of robotic applications.
Melexis brings reinforced isolation for its integrated current sensors
Melexis has announced a new safety qualification for the MLX91220 (5V) and MLX91221 (3V) current sensors. They can now be used in systems with higher voltage isolation requirements for both SOIC8 (715V BI, 307V RI) and SOIC16 (1415V BI, 707V RI) packages. This upgrade expands the application range and reduces the Bill of Material (BoM) component count. Applications requiring reinforced isolation include OBC and HVAC/compressor.
To guarantee the safety and isolation of high voltage class 3 energy sources, such as 800V EV battery packs and chargers, two isolation barriers must be implemented to reduce it to a low risk. Until now, the MLX91220 and MLX91221 had only been qualified as a basic (i.e. single) isolation device, mandating the need for an engineer to incorporate extra elements like an isolation amplifier into their design.
With the new UL/IEC 62368-1 certification (material group I), engineers can now use Melexis Hall-effect sensors, knowing its reinforced isolation is enough to safeguard the end user from high voltage risk without needing additional isolation barriers. The new voltage ratings are (for a pollution degree 2):
● for the SOIC16 package: 1415 V for basic isolation (BI) and 707 V for reinforced isolation (RI)
● for the SOIC8 package, 715 V for basic isolation (BI) and 307 V for reinforced isolation (RI)
Engineers currently using the MLX91220 or MLX91221 with an extra isolation barrier, can now eliminate the unnecessary isolation components. Additionally, for designs that currently have only basic isolation, it provides the possibility of re-qualifying as a reinforced isolated system without any change in the BoM.
The introduction of this ‘upgrade’, solely in the form of further technical qualification, improves the value of the Hall-effect sensors, streamlining designs and reducing the associated engineering efforts and costs. This solution not only maintains its accurate, flexible, and plug & play nature but also provides reinforced safety measures to diverse applications such as automotive on-board chargers (OBC), DC/DC converters, high voltage chargers, renewable energy inverters, white goods, and robotics.
The current sensors come in cost-effective and miniaturised SOIC8 narrow bodies with 4 mm creepage and larger SOIC16 wide-body packages with an 8 mm creepage. Both devices have a bandwidth of 300 kHz, a short response time of 2 us, and are available with a current range between 0-50 A RMS.
The MLX91220 and MLX91221 are available now.
Raspberry Pi server provides optimised and reliable solutions for industrial and IoT applications
Sfera Labs has announced the first shipments of its new Strato Pi Max flexible and expandable industrial controller based on the Raspberry Pi Compute Module (CM) 4.
The Strato Pi Max stands out with its modular design, DIN rail-mount, Wi-Fi and BLE wireless connectivity, dual Ethernet ports, dual SD, eMMC, and/or SSD storage options, and two USB ports. It’s a versatile module that can support up to four embedded expansion boards, expanding its capabilities to include serial (RS485/RS232) and CAN bus interfaces, digital I/O, additional wireless connectivity, and support for an uninterruptible power supply (UPS).
Strato Pi Max retains isolated RS-485 port, and USB ports with independent power control and fault detection built into existing members of the Strato Pi family and complies with all relevant industry standards for electrical safety, electromagnetic compatibility (EMC), and sustainability.
Strato Pi Max is offered in two versions: Strato Pi Max XS, which supports up to one expansion board, and Strato Pi Max XL, which supports up to four.
Both models embed pre-assembled CM4 boards with up to 8GB RAM and 32 GB eMMC and can be equipped with a high-performance M.2 PCIe SSD.
Strato Pi Max XL can be ordered in the Lite variant, offering enhanced data reliability with the optional dual SD card.
The Strato Pi Max’s modular architecture is a key feature, allowing it to be tailored to each project’s specific needs. The Strato Pi Max XL can support up to eight interfaces for CAN bus or Modbus, demonstrating its adaptability.
Based on open technology and fully compatible with the toolsets, programming languages, and development frameworks available for Raspberry Pi, the new module will allow designers to implement advanced control systems in industrial, commercial, and residential environments in a shorter timeframe and at a lower cost
https://sferalabs.cc/product/strato-pi-max-xl/
https://sferalabs.cc/product/strato-pi-max-xs/
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