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Infineon combines MEMS and automotive expertise for Xensiv microphone

Mon, Apr 19, 2021

High performance, low noise MEMS microphones are increasingly popular inside and outside of vehicles because of noise quality and hands-free operation. Infineon says it has combined its expertise in the automotive industry, with its MEMS microphones technical know-how to develop the Xensiv IM67D130A. It is claimed to be the first microphone in the market to be qualified for automotive applications.

The Xensiv IM67D130A microphone has a wide operating temperature range of -40C to +105 degrees C for use in harsh automotive environments. The high acoustic overload point (AOP) of 130dB sound pressure level (SPL) allows the microphone to capture distortion-free audio signals in loud environments, enabling it to be effective whether placed inside or outside of the vehicle. The IM67D130A can be used for in-cabin applications such as hands-free systems, emergency calls, in-cabin communication and active noise cancellation (ANC). For exterior applications, it can be used in, for example, siren or road condition detection. Its use allows sound to be a further, complementary sensor for advanced driver assistance systems (ADAS) and predictive maintenance.

The high signal-to-noise ratio (SNR) of 67dB combined with low distortion level are designed for optimum speech quality and speech intelligence for speech recognition applications. The microphones have tight sensitivity matching allowing optimised beamforming algorithms for multi-microphone arrays, added Infineon.

The Xensiv MEMS microphone IM67D130A is qualified for the AEC-Q103-003 standard for automotive applications and available now in PG-LLGA-5-4 package.

http://www.infineon.com

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Synopsys extends DesignWare IP to protect to ISO26262

Mon, Apr 19, 2021

Synopsys has extended the security levels in is DesignWare IP products to meet stringent safety process and documentation requirements for a broad range of applications for advanced driver assistance systems (ADAS), telematics, radar, voice to everything (V2X) communications and industrial SoCs.

The company has introduced the DesignWare tRoot hardware secure module (HSM) and ARC SEM130FS safety and security processor IP with integrated functional safety features to accelerate ISO 26262 certification of automotive SoCs.

The ASIL B compliant tRoot HSM for Automotive adds hardware safety mechanisms for protection against permanent, transient and latent faults to its security system that includes an ARC processor, scalable side-channel resistant cryptography, true random number generator and security-enabled external memory controllers.

The ASIL D-compliant ARC SEM130FS processor adds safety-critical hardware features such as dual-core lockstep to meet stringent automotive safety requirements. Both the ARC SEM130FS processor and tRoot HSM for Automotive are supported by safety documentation, including failure modes, effects and diagnostic analysis (FMEDA) reports that facilitate chip- and system-level ISO 26262 ASIL B or ASIL D compliance.

Designers need to implement increasingly advanced security and eliminate points of failure to combat increasing numbers of security attacks on safety-critical ADAS, telematics, radar, V2X communications and industrial systems. “By extending its DesignWare tRoot HSM and ARC SEM Processor IP solutions to include functional safety mechanisms, Synopsys is enabling designers to more easily deliver SoCs that meet their customers’ ASIL requirements and secure high-value data and communication from attacks,” said Wolfgang Ruf, product manager, semiconductors at SGS-TÜV Saar.

The Synopsys DesignWare tRoot HSM with Root of Trust provides designers with a trusted execution environment (TEE) as part of a pre-integrated, pre-verified safety and security solution. The tRoot HSM for Automotive also hardware redundancy, register error detection codes (EDC), memory error correction codes (ECC), watchdog timers and self-checking comparators for the entire system. In addition, the tRoot HSM for Automotive protects sensitive information and data processing in the connected car with features including secure boot, debug, firmware updates and key management.

The Synopsys DesignWare ARC SEM130FS Processor with Synopsys SecureShield technology helps designers to protect safety-critical systems against software, hardware and side-channel attacks with ASIL D compliance covering both random hardware faults and systematic development flow. Dual-core lockstep, ECC for memories and interfaces, transient fault protection for internal registers, diagnostic error injection and an integrated self-checking safety monitor are all integrated into the processor. The SEM130FS processor is supported by the certified ASIL D-compliant ARC MetaWare development toolkit to ease the development, debugging and optimisation of ISO 26262-compliant software. To help designers reach target ASILs, ARC FMEDA reports are available through the VC Functional Safety Manager, and the Z01X fault simulation solution offers a complete fault model set to meet ISO 26262 fault injection testing requirements.

The DesignWare ARC SEM130FS processor is scheduled to be available in Q2 2021 and DesignWare tRoot HSM for Automotive IP is scheduled to be available in Q3 2021.

http://www.synopsys.com

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MEMS barometric pressure sensors have lowest noise pressure, says TDK

Thu, Apr 15, 2021

Claimed to achieve the industry’s lowest pressure noise of 0.4 Pa RMS and attain the industry’s lowest power consumption of 1.3 microA, the InvenSense ICP-10125 is the latest addition to the SmartPressure family of TDK’s MEMS barometric pressure sensors.

The ICP-10125 also ensures temperature stability with a temperature coefficient of ±0.5 Pa per degrees C.

The ICP-10125 combines a barometric pressure and a temperature sensor in a small 3.55 x 3.55 x 1.45mm chimney package with waterproofing gel, providing IPX8 waterproofing to 10 ATM. The uniform machined lid and chimney with groove enable easier handling at production and assembly of customer products, says TDK. The ICP-10125 can be used in fitness, smart watch, and portable devices for fitness activity monitoring, location tracking for E911 calls, and indoor/outdoor navigation (dead-reckoning, floor/elevator/step detection).

The capacitive MEMS architecture delivers lower power consumption and lower noise than competing pressure sensors technologies, says TDK. It also has low noise and low power consumption, making the ICP-10125 suitable for wearable fitness monitoring and battery powered IoT. It can measure height change as small as 85mm, less than the height of a single stair step.

Operating temperature range is -40 to +85 degrees C.

“ICP-10125 delivers high accuracy, low power, temperature stability, and waterproofing in a small package footprint targeting the wearable market,” said Uday Mudoi, director of product marketing at InvenSense, a TDK company. “It enables determination of accurate location of E911 calls, tracks changes in elevation for activity monitoring, and extends battery life of always-on motion sensing applications.”

InvenSense ICP-10125 is available now for worldwide distribution. TDK also offers a development kit (DK-10125) and evaluation platform, as well as software to support customer development. The ICP-10125 joins the ICP-10101 and ICP-10111 pressure sensor products in the SmartPressure family.

InvenSense is a TDK Group company, providing MEMS sensors for consumer electronics and industrial areas with integrated motion and sound devices. Its portfolio combines MEMS sensors, such as accelerometers, gyroscopes, compasses, and microphones with proprietary algorithms and firmware that intelligently process, synthesise, and calibrate the output of sensors, maximising performance and accuracy.

InvenSense’s motion tracking, audio and location platforms, and services can be found in mobile, wearables, smart home, industrial, automotive, and IoT products.

InvenSense is headquartered in San Jose, California and has offices worldwide.

https://invensense.tdk.com

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Nvidia enters data centre arena with Grace CPU

Thu, Apr 15, 2021

Entering the data centre CPU arena, Nvidia has unveiled Grace, a server class processor for AI and high performance computing workloads. A system using the Arm-based processor, coupled with the company’s GPUs can deliver 10x faster than systems based on Nvidia’s DGX, which run on x86 CPUs.

The CPU was unveiled at GTC2021 this week. It is designed specifically for large scale AI and HPC for applications which analyse enormous datasets, requiring fast compute performance and large, low power memory subsystems, for example, natural language processing, recommender systems and AI supercomputing.

The fourth generation NVLink interconnect technology provide 900Bbyte/s connection between Grace and Nvidia GPUs to enable x30 higher aggregate bandwidth compared to today’s leading servers, claims the company.

The LPDDR5x memory subsystem is claimed to deliver twice the bandwidth and x10 better energy efficiency compared with DDR4 memory.

“Coupled with the GPU and DPU, Grace gives us the third foundational technology for computing, and the ability to re-architect the data centre to advance AI,” said founder and CEO, Jensen Huang at the launch during the company’s virtual GTC2021.

The processor combines energy-efficient Arm CPU cores with a low power memory subsystem to target workloads which can have over one trillion parameters – or “unthinkable amounts of data” said Huang, for niche computing in AI and data science.

Today’s largest AI models include billions of parameters, a number which is doubling every two and a half months, says Nvidia. Training them requires a new CPU that can be tightly coupled with a GPU to eliminate system bottlenecks. Grace uses Arm’s data centre architecture with its IP and licensing model.

The architecture provides unified cache coherence with a single memory address space, combining system and HBM GPU memory which is claimed to simplify programmability. Grace will be supported by the company’s HPC software development kit and the full suite of Cuda and Cuda-X libraries to accelerate more than 2,000 GPU applications.

Grace is expected to be available at the beginning of 2023.

The Swiss National Supercomputing Centre (CSCS) and the US Department of Energy’s Los Alamos National Laboratory have already announced plans to use Grace-powered supercomputers built by Hewlett Packard Enterprise. They are expected to be online in 2023. Los Alamos’director, Thom Mason, said the Grace CPU will be used to “deliver advanced scientific research using high-fidelity 3D simulations and analytics with datasets that are larger than previously possible”.

Appropriately, the CPU is named after Grace Hopper, the US Navy rear admiral and computer programmer scientist who developed the first computer language compiler.

https://nvidianews.nvidia.com

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Infineon combines MEMS and automotive expertise for Xensiv microphone

Synopsys extends DesignWare IP to protect to ISO26262

MEMS barometric pressure sensors have lowest noise pressure, says TDK

Nvidia enters data centre arena with Grace CPU

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