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Wideband mmWave 5G beamformers supports adding functionality

Mon, Aug 02, 2021

Fabless RF component company, Mobix Labs has the MBX10 True5G mmWave beamformer antenna in package (AIP) and its MIC600 single-chip, single-die beamformer IC.

The MBX10 is a 16-channel RF front end which includes all power amplifiers, low noise amplifiers, phase shifters, variable gain amplifiers, switches, and matching circuits with an integrated 2 x 2 antenna in package (7.5 x 7.5 x 1.8mm) that provides what Mobix Labs claims is “unprecedented levels of integration and scalability” in a cost-effective, bulk CMOS-based solution. The 16-channel support includes vertical, horizontal and circular polarisations and the 24 operating modes can transmit and receive on different frequencies simultaneously. They are scalable to meet any antenna array size requirement, says the company.

The Bulk CMOS technology allows the company to incorporate advanced functionality into a low-cost structure that can scale to meet the needs of any mmWave 5G system, said Fabian Battaglia, CEO of Mobix Labs. “We close the performance gap between Bulk CMOS and other manufacturing processes that gives customers looking to deploy 5G mmWave solutions a significant advantage in performance, efficiency, cost, size and time to market,” he said.

The MBX10 AIP and MIC600 Beamformer IC accelerate 5G mmWave network deployment and adoption in applications such as automotive, small cells, repeaters, access points, industrial IoT, medical, and consumer products.

The MBX10 and MIC600 are a single-chip, single-die Bulk CMOS solution offering worldwide coverage of 24.25 to 43.5GHz. They are claimed to offer superior thermal performance for improved efficiencies and better management of heat emissions.

Mobix Labs will be sampling the MBX10 and MIC600 to strategic customers by the end of Q3 2021.

Mobix Labs is a fabless semiconductor company, founded in 2020, based in Irvine, California, USA. It develops RF products for simplifying the design of next-generation 5G wireless products. The company manufactures compact, integrated, single-chip, single-die, CMOS-based mmWave beamformers, antenna solutions and RF semiconductors.

http://www.mobixlabs.com

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Developer kit accelerates AI vision

Mon, Aug 02, 2021

To accelerate proof of concept, rapid prototyping and small series production, Vision Components has collaborated with AU-Zone and Toradex to create the Maivin i.MX 8M Plus AI vision kit.

The developer kit is based on a Toradex Verdin i.MX 8M Plus system on module (SoM) and a carrier board designed by AU-Zone which accommodates up to two VC MIPI camera modules.

NXP’s i.MX 8M Plus processor has a neural network processor unit (NPU) and an integrated image signal processor. The Verdin SoM for the kit has been extended by a variable SoM adapter and connector board from AU-Zone, which enables users to build functional models. The VC MIPI IMX327-C (colour) and VC MIPI IMX296 (monochrome) camera modules are combined with the required interfaces and I/Os for individual rapid prototyping up to small series. Additional VC camera modules are also compatible. The AU-Zone connector boards can also be custom-developed with interfaces and functionalities for individual requirements. This makes the Maivin i.MX 8M Plus AI vision kit for a range of applications, including automation and robotics, medical technology or the agricultural industry. The kit also includes a housing, including lighting.

Drivers ensure optimal image processing, says Vision Components, which enable the direct connection and support of the VC MIPI camera modules with the NXP i.MX 8M processor family. They have been integrated into Toradex’ software platform, TorizonCore, which allows access to the image signal processor (ISP) of the i.MX 8M Plus. The ISP can be used for advanced image pre-processing such as colour conversion, geometry correction, HDR and gamma correction. The software platform also includes comprehensive frameworks for an easy entry into development, over the air updates and security features.

The kit also includes AU-Zone’s DeepView machine learning toolkit is also part of the Maivin i.MX 8M Plus AI vision kit. It includes machine learning demos for object recognition, classification, and tracking that can be customised to the users own AI models and datasets using the NXP eIQ toolkit. NXP continues to add tools to the development environment, including a GUI-based interface, and the DeepViewRT engine which is optimised for the i.MX platform. The company also added that other applications, for example AU-Zone applications, can be integrated and used to develop vision systems.

Vision Components drivers for the NXP i.MX 8M processor family are also available for platforms in addition to the Toradex Verdin SoM series platforms.

The kit is scheduled to be ready for shipping in Q3 2021.

http://www.vision-components.com

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Microchip unveils single chip for network synchronisation

Fri, Jul 30, 2021

Offering precise timing for 5G radio access equipment, the ZL3073x / 63x / 64x network synchronisation platform combines integration and performance in one compact, low-power device, says Microchip.

For 5G, time sources need to be synchronised throughout a packet-switched network 10 times more accurately than 4G requirements. The devices makes it possible to achieve 5G performance with what is claimed to be the first single chip, highly integrated, low power, multi-channel IC coupled with the company’s IEEE 1588 precision time protocol (PTP) and clock recovery algorithm software modules.

The ZL3073x / 63x / 64x network synchronisation platform implements sophisticated measure, calibrate and tune capabilities, which reduces network equipment time error to meet the most stringent 5G requirements, said Rami Kanama, vice president of Microchip’s timing and communications business unit.

Microchip’s measure, calibrate and tune capabilities ensure 5G systems achieve ITU-T Standard G.8273.2 Class C (30ns max|TE|) and the emerging Class D (5ns max|TEL|) time error requirements. The architecture offers up to five independent digital phase locked loop (DPLL) channels while consuming only 0.9W in a compact 9.0 x 9.0mm package that simultaneously reduces board space, power and system complexity.

There are five low-jitter synthesisers which offers 100 femto second root mean square (rms) jitter performance required by high speed interfaces in the latest 5G radio unit, distributed unit and central unit systems.

Microchip’s network synchronisation platform software includes its ZLS30730 high-performance algorithm coupled with its ZLS30390 IEEE 1588-2008 protocol engine. The network synchronisation platform combines seamlessly with Microchip’s family of precision 5G oscillators, adds the company. Its portfolio also includes clock generation, fanout buffer and jitter attenuator solutions as well as quartz and MEMS oscillators and Ethernet physical layer (PHY) devices.

A graphical user interface (GUI) and evaluation board are also available, along with application notes and other design-in support tools.

The ZL3073x / 63x / 64x network synchronisation platform is available in production quantities and offered with IEEE 1588 PTP and algorithm software modules, which are provided through license terms for download.

http://www.microchip.com

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Xtensa processors meet ISO 26262 compliance to ASIL-D

Thu, Jul 29, 2021

Cadence Tensilica Xtensa processors with FlexLock capability meet the ISO 26262:2018 standard to ASIL-D, the highest level possible under the Automotive Safety Integrity Level rating. The functional safety certification spans from base microcontroller to high-performance DSP, each with a configuration option for FlexLock to provide increased random fault protection. The processor have been developed following a robust safety process to protect against systematic faults. Tensilica Xtensa processors with FlexLock are suitable for the automotive market and tailored for AI, vision, radar, lidar, audio, vehicle-to-everything (V2X), and control applications.

The Cadence Tensilica FlexLock processors optimised for automotive applications are among the first in the industry to achieve full compliance with ASIL-D functional safety standards, said Wolfgang Ruf, head of functional safety for semiconductors at SGS-TÜV Saar. “Certification to . . . . the ISO 26262:2018 standard for ASIL-D systematic and random fault avoidance is a testament to the high functional safety quality of Cadence’s IP. SoC designers are assured that their designs using functional safety-certified Tensilica processor IP can achieve compliance with the automotive industry’s stringent safety-critical requirements,” he added.

Key to ASIL-D compliance is the new FlexLock capability, which adds lockstep support to the flexible and extensible Xtensa processor architecture. Lockstep is a proven method for increasing safety in software execution by providing redundancy of the core logic at the hardware level. In addition to ASIL-D certification, FlexLock also gives design teams the ability to accommodate two cores running independently in ASIL-B solutions and the option of running local memories and caches of two cores in lockstep, achieving even greater levels of protection against memory faults.

“Higher levels of autonomy require more intelligent computing at the edge in automotive applications, which is driving the need for higher levels of functional safety,” said Larry Przywara, senior group director, Tensilica marketing at Cadence. “With the introduction of FlexLock capability, users of Tensilica controllers and DSPs can achieve the highest level of certification, ASIL-D, and the protection it brings against random hardware faults. Designers choosing Tensilica IP to accelerate their ADAS [advanced driver assistance systems], radar, lidar, V2X and vision processing can do so with the confidence that they can meet their customers’ functional safety requirements.”

As with other Xtensa processors, the ASIL-D certified cores can be customised using the Tensilica Instruction Extension (TIE) language. This allows the IP to be optimised for the specific application, combining the right level of performance with the highest levels of safety.

The Tensilica Xtensa processors with FlexLock capability are available now.

http://www.cadence.com

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Wideband mmWave 5G beamformers supports adding functionality

Developer kit accelerates AI vision

Microchip unveils single chip for network synchronisation

Xtensa processors meet ISO 26262 compliance to ASIL-D

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