ClockMatrix network synchroniser reduces jitter on optical networks 

The second generation of ClockMatrix devices from Renesas Electronics build on the earlier synchronisers and jitter attenuators released by the company for 5G wireless and 100/200Gbits per second wireline network applications. The ClockMatrix 2 family of high-performance, precision, multi-channel timing devices are intended for 400/800Gbits per second optical transport and wireline network applications. They also improve on performance with phase jitter as low as 88fs rms.

The integrated devices provide all the functionality needed to implement an IEEE1588 clock solution with jitter attenuation capabilities, says Renesas, resulting in low jitter clock outputs for synchronous Ethernet PHYs with data rates up to 112Gbps PAM-4. They are also claimed to reduce design complexity and bill of materials (BoM) requirements, while allowing customers to apply the timing devices to a wide variety of network applications. 

The industry’s move to 5G is pushing the limits of network speed and precision and raising the bar on clock jitter and synchronisation capabilities, observed Bobby Matinpour, vice president of the Timing Products division at Renesas. 

The integrated, six-channel precision timing source eliminates the need for additional jitter attenuators for high-speed interfaces. The 88fs-rms phase jitter on clock outputs supports low jitter clock outputs for high-speed serial links (up to 112Gbits per second PAM-4 PHYs). The ClockMatrix 2 also supports multiple standards and protocols including synchronous Ethernet (Sync-E), and IEEE1588 and adheres to G.8262.1 and G.8262 telecomms boundary clock requirements and G.8273.2 Class C and Class D time accuracy. 

The RC32614A ClockMatrix 2 system synchroniser is available now. Optional PTP Clock Manager software is also available free of charge under license for use with the RC32614. 

Renesas Electronics delivers embedded design with microcontrollers, analogue, power and SoC products for automotive, industrial, infrastructure and IoT applications.

http://www.renesas.com

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S32G3 network processors extend to software-defined vehicle use

NXP Semiconductors has extended it S32G family of network processors with the S32G3 series. According to the company it now offers broad scalability from vehicle microcontrollers to higher-performance vehicle compute applications with software and pin compatibility.

There are four initial devices in the family, all software and pin-compatible with the S32G2 series which has been in full production since Q2 2021. They offer up to 2.5x more applications processing performance, on-chip system memory and networking than the current highest-performance S32G2 Series device. These capabilities allow them to enable more ECU consolidation and support intelligent software-defined vehicles, says NXP. 

The S32G3 processors have more Ethernet bandwidth on two ports and on-chip system memory than the current S32G2 Series’ highest-performance device (S32G274A). They also double the number of isolation domains, which are critical for future ECU consolidation. The package pinout remains the same.

An EVB3 evaluation board, RDB3 reference design and GoldBox 3 rugged enclosure version, combined with a broad range of enablement software and the Vehicle Integration Platform (GoldVIP) for rapid connected gateway development are available to support evaluation, development, proof-of-concept and to accelerate time-to-market. 

The addition of the new processors means that the S32G family now addresses a broader range of vehicle applications from safe microcontrollers to higher-performance domain controllers, safety processors and zonal vehicle compute applications. 

The emerging domain and zonal architectures require the integration of more processing, memory, networking bandwidth and resource isolation to support software-defined vehicles, advises NXP. Intelligent connected vehicles demand more complex advanced driver assistance systems (ADAS) safety and secure real-time and applications processing to offer vehicle and data-driven cloud services for smart cities and mobility. 

The S32G family of devices is supported by a broad partner ecosystem offering operating systems, virtualisation, execution environments, applications software, boards, software tools, engineering services, deep-dive training and cloud services. 

NXP helps customers design S32G system solutions with companion products. The SJA1110 multi-gigabit safe and secure automotive Ethernet switch is aligned to the latest TSN standards and offers integrated 100BASE-T1 PHYs, hardware-assisted security and safety capabilities and multi-gigabit interfaces. To ensure power management architecture and the safety concept scalability from S32G2 to S32G3, NXP developed the PF53 as a companion chip of the VR5510. The PF53 is a high-performance 12A core supply regulator with adaptive voltage positioning (AVP). 

NXP also offers a range of in-vehicle network transceivers with CAN high-speed signal integrity and security innovations.  

The initial S32G399A device has been sampled to lead customers with a production launch targeted for Q1 2023. 

http://www.NXP.com

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Infineon’s multi-protocol SoC complies to Matter, the smart home standard

Low power Airoc Bluetooth LE and 802.15.4 SoCs have been introduced by Infineon to help companies create low-power, high-performing products which comply to the Matter standard for smart homes. 

Infineon’s Airoc CYW30739 Bluetooth LE and 802.15.4 SoCs are secure and scalable and can connect low power devices in the smart home. The combination of complementary Bluetooth LE and 802.15.4 protocols not only enhances seamless interoperability but enables end-to-end encrypted communication between individual devices in a Matter network.

The SoC features a low-power radio and is claimed to offer superior RF performance for robust connections. The low power consumption supports applications that require extended battery life in smart homes, smart buildings and smart lighting systems, for example. 

The Airoc CYW30739 includes -95.5dBm LE Rx and -103.5dBm 802.15.4 sensitivity for long range Bluetooth and multi-protocol connectivity for seamless interaction between multiple connected devices. The integrated 96MHz Arm Cortex-M4 microcontroller has a floating point unit for computing performance as well as a highly optimised memory system across flash, RAM and ROM.

Infineon offers a comprehensive wireless portfolio to support Matter including the its Airoc Wi-Fi, Airoc Bluetooth and 802.15.4 and PSoC 6 microcontroller products. 

Developers can accelerate the deployment of Matter products by accessing Infineon’s software support for Matter in the open-source Matter repository. There are additional Matter-specific capabilities in Infineon’s ModusToolbox software and tools. The latest version of ModusToolbox is available now for download form the company’s website.

http://www.infineon.com

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SoC expands 5G radio unit performance, says Analog Devices

Radio unit developers can use the RadioVerse SoC to create the most energy efficient 5G radio units, says Analog Devices. 

The ADRV9040 is the first in the RadioVerse SoC series. It offers eight transmit and receive channels of 400MHz bandwidth and integrates advanced digital signal processing functions, including carrier digital up converters (CDUC), carrier digital down converters (CDDC), crest factor reduction (CFR) and digital pre-distortion (DPD). This expanded signal processing can eliminate the need for an FPGA, thereby reducing thermal footprint, and total system size, weight, power, and cost, advises Analog Devices. 

The SoC’s DPD algorithms were developed using advanced machine learning techniques and are optimised in close collaboration with major power amplifier (PA) vendors. The algorithms are fully tested and validated across 4G and 5G use cases, including various PA technology types such as gallium nitride (GaN). 

The SoC series provides advanced RF signal processing with expanded digital functionality and RF capacity designed to improve 5G radio unit performance and energy efficiency. The SoCs have been added to Analog Devices’ RadioVerse ecosystem. They combine Analog Devices’ Zero IF (ZiF) architecture with advances in functional integration and linearisation. The ZiF radio architecture simplifies RF filtering and signal chain components, reducing radio unit cost and development time for band and power variants designs, claims Analog Devices.

 Software defined RadioVerse transceivers are used in 4G and 5G RUs worldwide. Analog Devices has worked with Samsung to deploy 5G for some time. Dong Geun Lee, vice president and head of Hardware R&D Group, Network Business at Samsung Electronics, said: “We are excited for the successful launch of ADI’s new SoC, as we expect this cutting-edge technology will bring better 5G experience to consumers.”

Network operators are demanding power efficient radio units in the race to deploy the 5G infrastructure. With the exponential growth of wireless demand, energy efficiency is a key metric for operators as they seek to reduce their carbon footprint while expanding network capacity, says Analog Devices. The RadioVerse SoC series requires very low power compared to alternatives and implements advanced algorithms that deliver optimal radio unit system efficiency, says the company.

“RadioVerse SoCs are designed to optimise the full radio solution rather than just a single component or interface,” said Joe Barry, vice president of Wireless Communications at Analog Devices. “Each successive generation has provided expanded capabilities, bandwidth and performance, while improving overall [radio unit] efficiency. This new RadioVerse SoC series takes a big step forward by delivering multiple advancements in signal processing to meet the demanding needs of 5G,” he says.

http://www.analog.com

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