Silicon Labs brings AI and ML to the edge

Two families of 2.4GHz wireless SoCs are for Bluetooth and multiple-protocol operations with Matter-Ready Platform
The BG24 for Bluetooth and MG24 for multiple-protocols designs have been released, together with a software toolkit by Silicon Labs. The company says the co-optimised hardware and software platform will help bring AI/ML (artificial intelligence / machine learning) applications and wireless high performance to battery-powered edge devices.

The low power BG24 and MG24 SoCs incorporate PSA Level 3 Secure Vault protection, making them suitable for a range of applications in smart home, medical and industrial applications.

Together with what are believed to be the industry’s first integrated AI/ML accelerators, the 2.4GHz wireless SoCs have support for Matter, Zigbee, OpenThread, Bluetooth Low Energy, Bluetooth mesh, proprietary and multi-protocol operation. They also have the largest memory and flash capacity in the Silicon Labs portfolio, says the company.

The software toolkit helps developers to quickly build and deploy AI and ML algorithms using some of the most popular tool suites, like TensorFlow.
AI and ML has the potential to bring even greater intelligence to edge applications like home security systems, wearable medical monitors, sensors monitoring commercial facilities and industrial equipment, but there are performance and energy penalties for anyone considering deploying AI or ML at the edge, reports Silicon Labs.

The company has developed the BG24 and MG24 as the first ultra-low powered devices with dedicated AI / ML accelerators built-in to alleviate those penalties. The specialised hardware is designed to handle complex calculations quickly and efficiently, with internal testing showing up to a four times improvement in performance along with up to a six-fold improvement in energy efficiency. The ML calculations are performed on the local device rather than in the cloud, meaning that network latency is eliminated for faster decision-making and actions, says the company.

The large flash and RAM capacities mean that the device can evolve for multi-protocol support, Matter and trained ML algorithms for large datasets. PSA Level 3-Certified Secure Vault, the highest level of security certification for IoT devices, provides the security needed in products like door locks, medical equipment, and other sensitive deployments which required hardening the device from external threats.

In addition to native support for TensorFlow, Silicon Labs has partnered with AI and ML tools providers, SensiML and Edge Impulse, for a toolchain claimed to simplify the development of ML models optimised for embedded deployments of wireless applications. Developers can use the AI/ML toolchain with Silicon Labs’ Simplicity Studio and the BG24 and MG24 families of SoCs, to create applications that draw information from various connected devices, communicating with each other using Matter to then make intelligent ML-driven decisions.

An example of a target applications would be commercial office buildings, where lights are controlled by motion detectors that monitor occupancy- which are connected to audio sensors through the Matter application, so that someone sitting at a desk typing is not plunged into darkness because the additional audio data (the sound of typing) can be run through an ML algorithm for the lighting system to make a more informed decision about whether the lights should be on or off.

ML computing at the edge enables other intelligent industrial and home applications, including sensor-data processing for anomaly detection, predictive maintenance, audio pattern recognition for improved simple-command word recognition and vision use cases like presence detection or people counting with low-resolution cameras.

The single-die BG24 and MG24 SoCs combine a 78MHz Arm Cortex-M33 processor, 2.4GHz radio, 20-bit ADC, a combination of flash (up to 1536kbyte) and RAM (up to 256kbyte), and an AI/ML hardware accelerator for processing ML algorithms while offloading the Arm Cortex-M33.
The EFR32BG24 and EFR32MG24 SoCs are available in 5.0 x 5.0mm QFN40 and 6.0 x 6.0mm QFN48 packages. They are shipping today to alpha customers and will be available for mass deployment in April 2022. Multiple evaluation boards are available and modules based on the BG24 and MG24 SoCs will be available in the second half of 2022.

http://www.Silabs.com

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Tasking SmartCode environment supports Aurix microcontrollers

Developers focusing on the Aurix TC4x microcontroller family by Infineon can use Tasking’s SmartCode software development environment. 

The microcontroller family provides an upward migration path for the Aurix TC3x family. It features the next-generation TriCore 1.8 and scalable accelerators, including the parallel processing unit (PPU) as well as a single instruction, multiple data (SIMD) digital signal processor (DSP) to meet the requirements of various AI topologies, says Infineon.

The Aurix TC4x family supports developers in a range of automotive applications, including the future functional integration of domain- and zone-based E/E architectures. The microcontroller family can be used in electromobility and automated driving. 

The Tasking SmartCode supports both the next-generation Aurix TriCore v1.8 instruction set and the PPU AI accelerator. According to Tasking, SmartCode is the only productive development environment with compiler that supports all architectures in the Aurix TC4x (TriCore compiler, SCR compiler, GTM compiler and PPU compiler).

Tasking SmartCode is also suitable for the development of software in safety-critical applications in accordance with ISO26262 up to ASIL D. It also meets the cybersecurity requirements of the new ISO/SAE 21434:2021 standard. Tasking offers users the associated safety/security manual so that no additional costs are incurred for tool qualification.

According to Infineon’s senior vice president, Automotive Microcontroller, Thomas Böhm: “With Tasking’s comprehensive software development tools, our customers can optimise system performance and qualify their systems quickly and cost-effectively for an ASIL-D safety concept”.

Tasking Germany provides embedded software development tools. It is headquartered in Munich, Germany. 

Its development tools are used by automotive manufacturers and the world’s largest Tier 1 supplier to realise high-performance applications in safety-critical areas.  

Volume production of the Aurix TC4x series is planned for the end of 2024. Samples of the TC49x were received by lead customers in 2022. The first productive version of Tasking SmartCode is available now.

http://www.tasking.com

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Arrow Electronics and Appletec agree compact camera modules

Fast prototyping for new designs and re-engineering existing products is assured following an agreement signed by Arrow Electronics with Israeli company, Appletec. As a result, Appletec will produce a range of compact camera modules (CCMs) exclusively for Arrow. 

The CCMs are intended for developers who want to add an embedded vision capability to products used in sectors including industrial, medical, security and automotive. A customisation service will support a variety of interconnect solutions.

The choice of CCM will depend on a number of factors in the requirements of the application. For example, the amount of detail to be captured will determine the choice of resolution and frame rate, while the selected field of view (FOV) and depth of field will reflect the area to be covered.

The Arrow CCMs use CMOS image sensors from onsemi and can utilise the image signal processor (ISP) on the customer’s main board. Two fixed focus CCMs are available initially, offering 0.3 or 4Mpixel sensors and FoV ranging from 49 to 84 degrees. Frame rates range from 36.7 frames per second (at 720p) and 75 frames per second (at VGA) up to 360 frames per second. A CCM with auto-focus and 13Mpixel sensor will be added soon offering 30 frames per second and 64 degree FoV.

A fourth CCM, based on a 1.26Mpixel, 30 frames per second sensor has an integrated image flow processor, enabling vision functionality even for microcontroller platforms without additional hardware components.

System developers can write their own software drivers for the CCMs or make use of the driver produced by eInfochips, an Arrow company, which is due to be released at the end of Q1 2022.

Companies that wish to accelerate development times even deploy one of Arrow’s camera reference designs.

Arrow Electronics says it guides innovation forward for over 180,000 leading technology manufacturers and service providers. 

http://www.arrow.com

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Arm-based SoC and demo board are available to test Morello 

To test the Morello architecture, developed by Arm and the University of Cambridge, Arm has designed and developed an SoC and demonstrator board which contains the first example of the prototype architecture.  

The Morello programme has been a research initiative by a consortium led by Arm to design a new, inherently more secure, Arm-based computing platform. Arm has been collaborating with the University of Cambridge for several years on its CHERI Capability Hardware Enhanced RISC Instructions) architecture, which defines hardware capabilities that would provide a fundamentally more secure building block for software. 

The CHERI architectural extensions are designed to mitigate memory safety vulnerabilities, or software defects that are exploited by hackers to take control of a device or system – at a hardware level. CHERI augments pointers (the variables in computer code that reference where data is stored in memory) with limits as to how those references can be used, the address ranges that they can use to access and which functionality they can use to access.

These hardware capabilities are unique to the processor architecture. Once baked into silicon, they cannot be forged in software. Use of these capabilities in place of some or all the memory addresses can improve the spatial memory safety of software, particularly software written in C or C++ code.

These capabilities can also be used as a building block to allow the enforcement of much stronger temporal memory safety with potentially far lower overheads than current approaches to partitioning. Known as compartmentalisation, this process isolates different parts of critical code into individual ‘walled’ areas. Code operating within one compartment has no access to any other area; even if an attacker breaches one piece of the code or data, they are trapped within that one small zone.

These hardware capabilities will be fundamental in designing future devices that are resilient to memory corruption vulnerabilities and other forms of software-based exploitation, explained Arm.

The Morello prototype boards are ready for software developers and security specialists to start exploring the security advances possible with the Morello architecture.

The limited-edition boards are based on the Morello prototype architecture embedded into an Armv8.2-A processor (an adaptation of the Arm Neoverse N1 processor). The boards are being distributed to major stakeholders, such as Google and Microsoft, as well as to interested partners in industry and academia via the UKRI Digital Security by Design (DSbD) initiative to test the hypothesis of Morello and discover if this is a viable security architecture for businesses and consumers.

The Arm Morello research program aims to create a more secure hardware architecture for processors. Its architectural extensions are based on the CHERI protection model.

The Morello program aims to assess the viability of the prototype hardware SoC employing unique extensions to the conventional Arm hardware instruction set that improve device security. 

“Computers are incredibly useful but the price we pay for that utility is more and more exposure to security and privacy issues,” said Ben Laurie, principal engineer, Security, Google Research. “CHERI can allow for better, more cost-effective protection without reduced performance and Arm’s Morello prototype can help mitigate security issues showing the way to a better future for all computer users,” he said.

David Weston, director of Enterprise and OS Security at Microsoft, declared he is excited about the Morello project. “Memory safety exploits are one of the longest standing and most challenging problems in all of software security,” he said. “Using core silicon architecture to eliminate whole classes of security issues with minimal performance impact has the opportunity to be transformative with massive positive impact”.

The next two years will see the ecosystem testing, writing code and collaboratively providing critical feedback to determine whether any features will be used in future versions of the Arm architecture, said Arm. If the Morello prototype architecture performs as expected, it will be fundamental in future processor designs, protecting businesses, individuals and the devices of tomorrow.

http://www.arm.com

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