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At up to 2048bits of computation per cycle, Semidynamics says that its customisable Vector Unit is the largest available in the RISC-V market today, offering “unprecedented data handling”.

At the RISC-V Summit Europe 2023 (05 to 09 June) in Barcelona, Semidynamics highlights the customisable vector unit to accompany the company’s customisable 64-bit RISC-V cores. The Vector Unit complies with the RISC-V Vector Specification 1.0 and has additional, customisable features to enhance data handling capabilities. Semidynamics claimed that together they “set a new standard for data handling both in terms of unprecedented speed and volume”.

The company has taken the same approach with the Vector Unit as for its Atrevido core, which is not just configurable from a set of option but can be opened up and the inner workings changed to add features or special instructions to create a totally bespoke solution.

A Vector Unit is composed of several ‘vector cores’, roughly equivalent to a GPU core, that perform multiple calculations in parallel. Each vector core has arithmetic units capable of performing addition, subtraction, fused multiply-add, division, square root, and logic operations. Semidynamics’ vector core can be tailored to support different data types: FP64, FP32, FP16, BF16, INT64, INT32, INT16 or INT8, depending on the customer’s target application domain. The largest data type size in bits defines the vector core width or ELEN. Customers select the number of vector cores to be implemented within the Vector Unit, either four, eight, 16 or 32 cores, catering for a wide range of power performance area (PPA) trade-off options. Once these choices are made, the total Vector Unit data path width or DLEN is ELEN multiplied by the number of vector cores. Semidynamics supports DLEN configurations from 128b to 2048bits.

Semidynamics has equipped its Vector Unit with a high performance, cross vector core network that provides all-to-all connectivity between the vector cores at high bandwidth, even for the very large, 32-vector core option. The cross vector core unit is used for specific instructions in the RISC-V standard that shuffle data between the different vector cores, such as vrgather or vslide.

A second choice is the number of bits of each vector register (VLEN) which can also be tailored to customer’s needs. Most vendors assume that VLEN is equal to DLEN (i.e., 1X ratio), Semidynamics offers 2X, 4X and 8X ratios. When the VLEN is larger than the DLEN, a vector operation uses multiple cycles to execute. This allows the Vector Unit to tolerate large memory latencies and reduce power. For example, when VLEN=2048 and DLEN=512, each vector arithmetic operation will take four clocks to execute. As a result, the Vector Unit can process “unprecedented amounts of data bits” and fetch all this data from memory. Semidynamics’ Gazzillion technology can handle up to 128 simultaneous requests for data and track them back to the correct place in whatever order they are returned. This level of fast handling of big data is expected to be beneficial in application areas such as HPC (high performance computing) application areas such as video processing, AI and ML.

If required, Semidynamics can do Open Core Surgery on cores and Vector Units to provide special interfaces and protocols to a customer’s proprietary IP block.

Founded in 2016 and based in Barcelona, Spain, Semidynamics provides fully customisable RISC-V processor IP and specialises in high bandwidth, high performance cores with vector units targeted at ML and AI applications. The company is privately owned and is a strategic member of the RISC-V Alliance.

http://www.semidynamics.com