Commercial interconnect IP from Arteris IP, is claimed to accelerate the development of next-generation deep neural network (DNN) and machine learning systems. The FlexNoC version 4 interconnect IP and the companion AI Package. FlexNoC 4 and the AI Package (FlexNoC 4 AI) implement new technologies that ease the development of today’s most complex AI, deep neural network (DNN), and autonomous driving SoCs, explains Arteris.
Arteris IP created the new technologies in FlexNoC 4 AI based on its learning from customers, including Mobileye, which recently licensed Arteris IP FlexNoC and Ncore interconnect IP for its next-generation EyeQ systems.
Using automated topology generation for mesh, ring and torus networks, the FlexNoC 4 AI enables SoC architects to generate AI topologies automatically and also edit generated topologies to optimise each individual network router, if desired.
The FlexNoC 4 AI intelligent multicast optimises the use of on-chip and off-chip bandwidth by broadcasting data as close to network targets as possible. This allows for more efficient updates of DNN weights, image maps and other multicast data.
Another feature, source synchronous communications, helps avoid clock tree synthesis, physical placement, and timing closure problems when spanning long distances on AI chips, which can be larger than 400mm2.
The VC-Link virtual channels allow long physical links to be shared in congested areas of the die while maintaining quality of service (QoS).
There is also support for HBM2 and multichannel memory and for up to 2048-bit wide data.
The FlexNoC 4 interconnect IP and the FlexNoC 4 AI Package are available immediately.
Arteris IP provides network in chip (NoC) interconnect IP to accelerate SoC semiconductor assembly for a range of applications from artificial intelligence (AI) to automobiles, mobile phones, IoT, cameras, SSD controllers, and servers. Its customer base include Samsung, Huawei, HiSilicon, Mobileye and Texas Instruments. The IP product line can help customers obtain lower power, higher performance, more efficient design reuse and faster SoC development, to lower development and production costs.
