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Two Xeon processor additions target HPC and AI

Tue, Nov 06, 2018

Intel announces two member of its Xeon processor portfolio. The Cascade Lake advanced performance processor is expected to be released the first half of 2019 and the Intel Xeon E-2100 processor for entry-level servers is available now.

Cascade Lake represents a new class of Intel Xeon Scalable processors designed for the most demanding high-performance computing (HPC), artificial intelligence (AI) and infrastructure-as-a-service (IaaS) workloads. The processor incorporates a performance optimised multi-chip package to deliver up to 48 cores per CPU and 12 DDR4 memory channels per socket.

Cascade Lake advanced performance processors will deliver both core CPU performance gains and leadership in memory bandwidth constrained workloads, promises Intel. Performance estimates include Linpack up to 1.21x versus Intel Xeon Scalable 8180 processor and 3.4×2 versus AMD EPYC 7601; Stream Triad up to 1.83x versus Intel Scalable 8180 processor and 1.3×2 versus AMD EPYC 7601;

AI/deep learning inference up to 17x images-per-second versus Intel Xeon Platinum processor at launch.

Intel SGX on the Intel Xeon E-2100 processor family delivers hardware-based security to secure customer data and applications. This feature allows new entry-level servers featuring an Intel Xeon E-2100 processor to provide an additional layer of hardware-enhanced security measures when used with properly enabled cloud applications.

The Xeon E-2100 processor is targeted at small- and medium-size businesses and cloud service providers. It supports workloads suitable for entry-level servers as well as any computing applications requiring enhanced data protection for sensitive workloads.

The Intel Xeon E-2100 processor-based servers will support the latest file-sharing, storage and backup, virtualisation, and employee productivity solutions.

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http://www.intel.com

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SoCs now support Bluetooth mesh standard

Mon, Nov 05, 2018

The addition of the Bluetooth mesh networking standard to the RSL10 Bluetooth 5 Radio SoCs, introduces mesh networking and new development support, says ON Semiconductor.

Standardised Bluetooth mesh networking is now supported with the ON Semiconductor Mesh release, enabling many-to-many device communications. Device manufacturers can deploy large-scale, low-power Bluetooth mesh networks for smart homes, building automation and asset tracking.

The ON Semiconductor RSL10 Mesh release is claimed to have the industry’s lowest power consumption. It consumes just 62.5nW in deep sleep mode and seven milliwatts (mW) peak receive power to preserve battery life. The RSL10 radio’s energy efficiency was recently validated by the EEMBC’s ULPMark where it became the first device to break 1,000 ULP Marks, and produced Core Profile scores more than twice those of the previous industry leader, reports ON Semiconductor.

Prototyping and testing of Bluetooth Low Energy peripherals for node-to-node and mesh connectivity is now easier with the RSL10 USB Dongle. ON Semiconductor’s BLE Explorer software applications and the RSL10 USB Dongle enables developers to scan, connect, and wirelessly interact with prototypes while monitoring and logging behaviour.

The RSL10 Bluetooth Mesh package is available now.

ON Semiconductor supplies energy efficient, power management, analogue, sensors, logic, timing, connectivity, discrete, SoC and custom devices. The company’s products help engineers in automotive, communications, computing, consumer, industrial, medical, aerospace and defence applications. ON Semiconductor has a network of manufacturing facilities, sales offices and design centres in key markets throughout North America, Europe and the Asia Pacific regions.

This news story is brought to you by softei.com, the specialist site dedicated to delivering information about what’s new in the electronics industry, with daily news updates, new products and industry news.

To stay up-to-date, register to receive our weekly newsletters and keep informed of the latest technology news and new products from around the globe. Simply click this link to register here: softei.com

Readers can also register to receive the monthly newsletter from our sister site, weartechdesign.com. This is the only website dedicated to developers of wearable electronic products. Simply click this link to register: weartechdesign.com

We have a Fitbit to give away on both Softei.com and Weartechdesign.com! Register today to enter the competition to win a Fitbit at softei.com or weartechdesign.com.

http://www.onsemi.com

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Development of a smart city concept at Munich Airport

Mon, Nov 05, 2018

Munich Airport and the renowned Senseable City Lab at the Massachusetts Institute of Technology (MIT) have reached an agreement to work together in the development of the LabCampus Innovation Center at Munich Airport.

Plans to launch the LabCampus future project–an innovation lab on the airport campus that will promote cooperation between companies and across industry boundaries–were announced by Munich Airport in March of this year. Starting on November 1, the renowned Senseable City Lab, at the Massachusetts Institute of Technology (MIT), will be on board to provide conceptual support for the establishment and development of the new innovation campus. Under an initial three-year cooperation agreement, the MIT Senseable City Lab, based in Cambridge, MA, will act as a research partner, supporting the team in Munich as it turns the campus into an innovative smart city. The goal is to build an ideal urban environment offering optimal conditions for people and companies to work together efficiently, creatively and–above all–under one roof. This will provide a setting to design and develop products and services for the world of the future and to test them onsite. To make this a reality, LabCampus GmbH will work with MIT to establish a future-ready infrastructure right from the start, focusing on state-of-the-art technologies in the areas of energy, mobility and urban planning as well as the connectivity between them for optimal sustainability and livability for the users.

“This cooperation is a major milestone for our innovation site,” says Dr. Marc Wagener, Managing Director of LabCampus GmbH. “We will be working with MIT researchers to study and evaluate the most important trends and digital technologies that can benefit us in the development and successful implementation of a smart city concept.” Prof. Carlo Ratti, Director of the MIT Senseable City Lab is also delighted: “This is an excellent opportunity for us to be involved in creating a smart city from the earliest stages. It gives us a chance to look ahead and weave everything, including future needs, into the infrastructure from the very beginning.”

MIT Senseable City Lab is the first global player outside of Europe to sign a cooperation agreement with LabCampus GmbH. Research institutions that have signed on as innovation partners include FAU Erlangen-Nuremberg and the Hasso Plattner Institute as well as the Fraunhofer Institute, which is also exploring the possibility of renting space at LabCampus. LabCampus is engaged in detailed talks with other international groups, too. For more information: www.labcampus.de

Caption: Dr. Marc Wagener (left), Managing Director of LabCampus GmbH and Professor Carlo Ratti, Director of MIT Senseable City Lab, signing a cooperation agreement on November 1, 2018 (Copyright: Munich Airport)

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IP innovates with visually lossless image compression for GPUs

Fri, Nov 02, 2018

Providing a reduction in memory footprint, Imagination Technologies has announced PowerVR PVRIC4 technology which provides cost savings for memory and bandwidth-constrained devices such as DTVs, smartphones and tablets.

The company explains that its new generation of powerful image compression technology will enable SoC to reduce costs without a discernable loss of image quality. PVRIC4 enables random-access visually lossless image compression, ensuring bandwidth and memory footprint savings of at least 50 per cent, confirms Imagination, and enables systems to overcome performance bandwidth constraints.

PVRIC4 is provided as a standalone IP block for SoC manufacturers, already used by partners.

PVRIC4 features a dual-pipeline framebuffer compression engine. A new lossy pipeline, used only if the lossless pipeline does not achieve 50 per cent compression, ensures that even difficult to compress ‘noisy’ images are compressed with the highest fidelity. A decision logic block determines which output should be used to guarantee the compression ratio, and highly tuned algorithms ensure the image quality change is imperceptible. The hybrid solution offers SoC manufacturers high fidelity ensuring bandwidth and frame buffer allocation savings on graphics and video content, says the company, all performed in hardware and achieved without any performance overhead.

PVRIC4’s bandwidth savings translate into better battery life and cost savings for system manufacturers. RAM and bandwidth can be freed for other uses, such as enabling simultaneous fast 5G downloads while the GPU is in use, or a reduction in the number of DRAM devices used in the system.

PVRIC4 will be available as a feature in next-generation PowerVR GPUs and is available for licensing now as a standalone IP block.

Imagination Technologies provides a range of silicon IP (intellectual property) including key processing blocks needed to create the SoCs that power all mobile, consumer and embedded electronics.

Imagination Technologies was acquired in 2017 by Canyon Bridge, a California-headquartered, global private equity investment fund.

http://www.imgtec.com

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Two Xeon processor additions target HPC and AI

SoCs now support Bluetooth mesh standard

Development of a smart city concept at Munich Airport

IP innovates with visually lossless image compression for GPUs

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