Lens array for optical transceivers include mirror

Optical networks for data centres can maximise density in optical transceivers using the FLHL2 series lens array with mirror from Alps Alpine.

IoT technology and artificial intelligence (AI) has increase IP traffic globally. This is expected to be increased further by the introduction of 5G mobile and wireless networks. As a result, optical transceivers used in facilities like data centres will need to be much faster and have higher density, demanding even greater size reductions and high-density mounting of components.

The FLH2 series was developed by Alps Alpine in responses to these trends. The lens array has a 0.75mm lens pitch and integrates condenser lens and mirror components of an optical transceiver receiver. The array measures just 1.3 x 1.3 x 3.5mm. Now, instead of have to position the lenses and mirror separately to convey light to the photodiode, this integrated lens reduces the number of parts and shortens the optical distance to contributing to downsizing the optical transceivers. Having fewer components also reduces the work required for transceiver assembly, leading to lower costs, adds Alps Alpine.

The lead-free glass used is (RoHS-compliant).

Mass production will begin in August this year and Alps Alpine has also announced that it will develop lens arrays with 0.5mm and 0.25mm lens pitches in anticipation of future market requirements for downsizing and multi-channel transceivers as IoT spreads and 5G services are introduced.

Alps Alpine developed one of the world’s smallest glass lenses for submarine cables in 2000.

Alps Alpine was formed on January 1, 2019, when Alps Electric and Alpine Electronics integrated. The company has over 42,000 employees.

Alps Alpine has expertise in core devices, system design and software development and serves the automotive, mobile devices and consumer electronics markets, as well as new sectors such as energy, healthcare and industry.

http://www.alpsalpine.com

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Rutronik UK supports STM32MP1 processor

System memory for the recently introduced STM32MP1 multi-core microprocessor series includes compute and graphics support combined with power-efficient real-time control. The aim is to aid the development of high-performance solutions for industrial, consumer, smart home, health and wellness applications.

Rutronik UK has combined STM32MP1 technology with approved technology partners Nanya in the form of a 4Gbit DDR3L SDRAM 16-bit and also Toshiba Memory’s 4GByte eMMC. The multi-core microprocessors and the memories, recommended by ST, are available from the distributor.

Engineers can used the STM32MP1 microprocessor series to develop a range of applications using the new heterogeneous architecture that combines up to two Arm Cortex-A7 and a Cortex-M4 core. This flexible architecture performs fast processing and real-time tasks on a single chip, always achieving the greatest power efficiency, reports Rutronik UK. The STM32MP1 embeds a 3D graphics processor unit (GPU) to support human machine interface (HMI) displays.

Rutronik also offers an evaluation board, the STM32MP157C-EV1 and two Discovery kits, the STM32MP157A-DK1 and STM32MP157C-DK2.

A firmware package, STM32CubeMX, is designed for software and hardware configuration of both the Cortex-A7 and Cortex-M4 cores. It handles C-code generation for the M4 core, DDR SDRAM interface configuration, and tuning tool. It can also generate Linux device trees.

Rutronik UK operates as an independent company in the UK. Its parent company, Rutronik Elektronische Bauelemente, is a broadline distributor for semiconductors, passive and electromechanical components in addition to storage technologies, displays and boards and wireless products. The markets that the company primarily targets include automotive, medical, industrial, home appliance, energy and lighting. It also offers support in the areas of product development and design, individual logistics and supply chain management.

http://www.rutronik.com

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eSilicon announces production of FinFET ASIC for 5G infrastructure

A large 2.5D FinFET ASIC targeting the 5G infrastructure market is entering final product qualification, announces eSilicon. The company has collaborated with the ASE Group for packaging, Rambus for the high-performance SerDes, Samsung for the 14nm FinFET ASIC fabrication and HBM memory stacks and UMC for the silicon interposer.

The design, which is over 600mm2, contains multiple HBM2 memory stacks on a silicon interposer, employs over 100 lanes of SerDes and contains over 800Mbit of embedded SRAM.

“Designs of this size require specialised analysis and materials, so collaboration between ecosystem players has become more crucial than ever,” said Calvin Cheung, vice president of engineering at ASE Group.

“Rambus’ high performance and flexible SerDes technology, with a large number of SerDes lanes running at various speeds, is a key enabler for this complex ASIC,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are excited to collaborate with our ecosystem partners on the strategic elements to drive the next-generation 5G network growth.”

“This is one of the largest dies we have produced in this 14nm node,” said Hong Hao, senior vice president of Foundry Marketing at Samsung Semiconductor.

Pablo Temprano, Samsung Semiconductor’s vice president of memory marketing added: “The 5G market will mark a new era of technological efficiency for which this 2.5D FinFET ASIC is set to help lead the way.”

“Many 5G designs will require 2.5D technology with a silicon interposer,” said Walter Ng, vice president of sales at UMC. “UMC’s technology provides a critical enabler for these designs.”

Ajay Lalwani, vice president of global manufacturing operations at eSilicon, explained: “Getting this design into production was a real team effort between eSilicon and our ecosystem partners. This teamwork, and the resultant success of this complex part in the end system is the new definition of ASIC success.”

eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Its ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimised 16, 14 or 7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialised memory compilers and I/O libraries. eSilicon’s neuASIC platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets.

http://www.esilicon.com

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Programmable PMIC increases ADAS reliability

Space can be saved in advanced driver assistance systems (ADAS) and reliability increased with the L5965 power management integrated circuit (PMIC), says ST Microelectronics.

The seven-output automotive PMIC enables more compact and reliable electronic control units leveraging direct operation from battery voltage with register-programmable output voltages and sequencing and integrated functional-safety mechanisms, explains ST Microelectronics.

With seven regulated outputs, a single L5965 can power an entire camera- or radar-based driver-assistance system including the sensors, memory ICs, processor, and CAN interface circuitry. One-time programmable (OTP) cells for setting the output voltages and sequencing allow the user to configure the PMIC for a variety of ADAS and other in-car applications.

The L5965 can operate directly from the vehicle battery which allows its use without a pre-regulator. Its register-programmable outputs also eliminate voltage setting resistors, and the on-chip regulators can be used without external compensation circuitry.  The PMIC reduces both footprint and bill of materials. The savings in external components also increase system reliability and enhance accuracy, explains ST Microelectronics, by eliminating fluctuation due to environmental effects on external components.

The integrated functional-safety features are designed in compliance with ISO 26262 and enable systems to fulfil Automotive Safety Integrity Level (ASIL) requirements up to ASIL-D. The mechanisms include a failure status pin, voltage monitors, ground-loss comparators, analogue and digital built in self-test (BIST), and temperature monitors.

Samples of the L5965 are available now in a small and low-cost 7.0 x 7.0mm QFN48 package that requires no heatsink.

http://www.st.com

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