Sector News

Microchip has entered the memory infrastructure market, offering what it claims to be the first commercially serial memory controller for artificial intelligence (AI) and machine learning (ML).

The SMC 1000 8x25G enables four times the memory channels of parallel-attached DDR4 DRAM and low latency, says Microchip. It has been introduced as the computational demands of AI and ML workloads accelerate, highlighting the shortfall in DRAM, which require an increased number of memory channels to deliver more memory bandwidth.

The SMC 1000 8x25G enables CPUs and other compute-centric SoCs to use four times the memory channels of parallel attached DDR4 DRAM within the same package footprint. This enables serial memory controllers to deliver higher memory bandwidth and media independence to these compute-intensive platforms with low latency.

As the number of processing cores within CPUs has risen, the average memory bandwidth available to each processing core has decreased because CPU and SoC devices cannot scale the number of parallel DDR interfaces on a single chip to meet the needs of the increasing core count. The SMC 1000 8x25G interfaces to the CPU via 8-bit Open Memory Interface (OMI)-compliant 25Gbits per second lanes and bridges to memory via a 72-bit DDR4 3200 interface. This formation reduces the required number of host CPU or SoC pins per DDR4 memory channel “significantly”, says Microchip, allowing for more memory channels and increased memory bandwidth.

The SMC 1000 8x25G is the first memory infrastructure product in Microchip’s portfolio that enables the media-independent OMI.

Data centre application workloads require OMI-based differential dual-inline memory modules (DDIMMs) to deliver the same high-performance bandwidth and low latency results of today’s parallel-DDR based memory products. The low latency of the SMC 1000 8x25G delivers less than four nanoseconds incremental latency to the first DRAM data access and identical subsequent data access performance, reports Microchip. OMI-based DDIMM products have virtually identical bandwidth and latency performance to comparable LRDIMM products, concludes the company.

A CPU or SoC with OMI support can use various types of media, allowing designers to select appropriate cost, power and performance metrics without having to integrate a unique memory controller for each type. Microchip points out that CPU and SoC memory interfaces today are typically locked to specific DDR interface protocols, such as DDR4, at specific interface rates.

SMART Modular, Micron and Samsung Electronics are building multiple pin-efficient 84-pin DDR4 DDIMMs with capacities ranging from 16 to 256Gbyte. These DDIMMs will leverage the SMC 1000 8x25G and will seamlessly plug into any OMI-compliant 25Gbits per second interface, Microchip advises.

The SMC 1000 is supplied with ChipLink diagnostic tools that provide extensive debug, diagnostics, configuration and analysts tools with an intuitive graphics user interface (GUI).

The SMC 1000 8x25G is sampling now.

http://www.microchip.com