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Intel ships 10nm Agilex FPGAs for networking, 5G and data analytics

Mon, Sep 02, 2019

Shipments have commenced for the Intel Agilex field programmable gate arrays (FPGAs). The devices are being used by early access program customers to develop advanced solutions for networking, 5G and accelerated data analytics.

Participants in the early access program include Colorado Engineering, Mantaro Networks, Microsoft and Silicom.

Dan McNamara, Intel senior vice president and general manager of the Networking and Custom Logic Group, said that the Agilex FPGA family leverages architecture, packaging, process technology, developer tools and a fast path to power reduction with eASIC technology to enable new levels of heterogeneous computing, system integration and processor connectivity. It will be the first 10nm FPGA to provide cache-coherent and low latency connectivity to Intel Xeon processors with the upcoming Compute Express Link, he added.

The Agilex FPGAs are expected to provide the agility and flexibility that is demanded by data-centric, 5G-fuelled operations where networking throughput must increase and latency must decrease. Intel Agilex FPGAs deliver “significant gains in performance and inherent low latency,” says the company. They are reconfigurable and have reduced power consumption, together with computation and high-speed interfacing capabilities that enable smarter, higher bandwidth networks to be created. They also contribute to delivering real-time actionable insights via accelerated artificial intelligence (AI) and other analytics performed at the edge, in the cloud and throughout the network.

According to Doug Burger, technical fellow, Azure Hardware Systems at Microsoft, the software company has been working closely with Intel on the development of the Agilex FPGAs and is planning to use them in accelerating real-time AI, networking and other applications/infrastructure across Azure Cloud Services, Bing and other data centre services.

The Intel Agilex family combines second-generation HyperFlex FPGA fabric built on Intel’s 10nm process, which is up to 40 per cent higher performance or up to 40 per cent lower total power compared with Intel Stratix 10 FPGAs. There is also the heterogeneous 3D silicon-in-package (SiP) technology based on Intel’s proven embedded multi-die interconnect bridge (EMIB) technology. As a result, Intel can integrate analogue, memory, custom computing, custom I/O and Intel eASIC device tiles into a single package along with the FPGA fabric.

Intel also says they are the only FPGAs that support hardened BFLOAT16, with up to 40TFLOPS of digital signal processor (DSP) performance. They also have the ability to scale for higher bandwidth compared with PCIe Gen 4, due to the use of PCIe Gen 5.

Transceiver data rates support up to 112Gbits per second for high-speed networking requirements for 400GE and beyond. There is also support for memory option, such as current DDR4, upcoming DDR5, HBM, and Intel Optane DC persistent memory.

Design development support for Intel Agilex FPGAs is available today via Intel Quartus Prime Design Software.

http://www.intel.com

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Congatec introduces rugged data processing engines for oil and gas

Tue, Aug 27, 2019

Robust embedded edge server platforms for the energy sector will be introduced by congatec at SPE Offshore Europe next month (3 to 6 September).

The oil and gas industry is characterised by distributed assets and infrastructures in harsh environments and therefore require ultra-robust embedded platforms for the digital transformation challenge that offers a huge potential for cost savings.

Digitisation could reduce production costs by up to 30 per cent, estimates the International Energy Agency, with potential savings through efficient maintenance and better operation of assets. “There is also further potential for savings in the supply chain, through the use of artificial intelligence (AI) and integrated platforms that connect organizations with external partners,” explains Dan Demers, director sales and marketing at congatec Americas.

To meet the requirements of the upstream and mid-stream oil and gas industry, congatec’s embedded edge computing platforms are designed for extended temperature ranges, with optional conformal coating to protect against the effects of salt water or condensation caused by large temperature fluctuations. They also offer comprehensive server class reliability, availability, serviceability (RAS) features that enable OEMs to reliably manage thousands of devices remotely. As multi-core designs with currently up to six cores and a particularly low 25W thermal dynamic performance (TDP), they are suitable for completely fanless – and therefore maintenance-free – 24/7 operation in hermetically sealed housings with the highest IP protection classes, says congatec. Virtual machines based on Real-Time Systems’ hypervisor technologies allow optimal use of existing computing resources by partitioning the various tasks – including local real-time control requirements.

Virtualisation also means that the new platforms are tailored to build cost-efficient universal customer premises Equipment (uCPE). Such open standard hardware equipment is characterised by hosting telecomms network functions at the customers edge IT including software defined networks (SDN) and network functions virtualisation (NFV).

Visit congatec at SPE Offshore Europe, Aberdeen, Scotland, 3 to 6 September, Hall 1, stand 1AA62.

http://www.congatec.com

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“World’s largest chip” has more compute cores for data access

Thu, Aug 22, 2019

Claimed to be the largest chip in the world, the Cerebras wafer scale engine (WSE) measures 216 x 216mm (8.5 x 8.5 inch). At 46,225mm² the chip is 56x larger than the biggest graphics processing unit (GPU) ever made, claims Cerebras.

It has 400,000 cores and 18Gbyte on-chip SRAM. The large silicon area, more than the largest graphics processing unit, enables the WSE to provide more compute cores, tightly coupled memory for efficient data access, and an extensive high bandwidth communication fabric for groups of cores to work together, claims Cerebras.

The WSE contains 400,000 sparse linear algebra (SLA) cores. Each core is flexible, programmable, and optimised for the computations that underpin most neural networks. Programmability ensures the cores can run all algorithms for constantly changing machine learning operations.

The cores on the WSE are connected via the Swarm communication fabric in a 2D mesh with 100 petabytes (Pbytes) per second of bandwidth. The Swarm on-chip communication fabric delivers breakthrough bandwidth and low latency at a fraction of the power draw of traditional techniques used to cluster GPUs, says Cerebras. It is fully configurable. Software configures all the cores on the WSE to support the precise communication required for training the user-specified model. For each neural network, Swarm provides an optimised communication path.

The 18Gbyte of on-chip memory is accessible within a single clock cycle, and provides 9 Pbytes per second memory bandwidth. This is 3,000 times more capacity and 10,000 times greater bandwidth than the leading competitor, claims Cerebras. The WSE provides moree cores, more local memory and enables fast, flexible computation, at lower latency and with less energy than other GPUs, concludes Cerebras.

https://www.cerebras.net/technology/

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Porsche invests in Israeli startup TriEye to increase road visibility and safety

Wed, Aug 21, 2019

Israeli startup TriEye, whose Short-Wave-Infra-Red (SWIR) sensing technology enables vision in adverse weather and night-time conditions, has expanded its Series A round to $19 million with an investment from the German sports car manufacturer Porsche. The additional funding will be used for ongoing product development and operations, as well as team growth.

In May 2019, TriEye announced a Series A funding round, led by Intel Capital. Other investors in the round include Marius Nacht and TriEye’s existing investor Grove Ventures. Since its inception, TriEye has raised $22 million, including a seed investment of $3 million led by Grove Ventures in November 2017.

Porsche Ventures seeks strategic investments in business models relating to customer experience, mobility and digital lifestyle, as well as in future technologies such as artificial intelligence, blockchain and virtual and augmented reality. Through its venture capital activities, the sports car manufacturer Porsche invests in new companies that are in the early and growth phases.

TriEye was founded in 2017 by Avi Bakal (CEO), Omer Kapach (VP R&D) and Prof. Uriel Levy (CTO), after nearly a decade of advanced nanophotonics research by Prof. Levy at the Hebrew University in Jerusalem. The company has succeeded in developing an HD SWIR camera that is a smaller size, higher resolution, and a fraction of the price of current technologies. TriEye already succeeded in proving that the technology works and can be mass-produced.

The company’s CMOS-based Raven camera, whose initial samples are due to launch in 2020, is designed to save lives on the roads. Once integrated, the camera will allow ADAS and AV to achieve unprecedented vision capabilities under common adverse weather and low-light conditions such as fog, dust or night-time.

As ADAS systems are expected to operate under a wider range of scenarios, car manufacturers and their suppliers (OEMs and Tier 1s) are realizing that SWIR plays a key role in ADAS and AV sensor fusion in order to achieve full visibility under any weather or lighting conditions. Driving tests and research have shown that even when fusing other sensing solutions such as radar, lidar, and standard cameras, the fusion solution fails in solving the low visibility challenge.

“TriEye is a promising technology company led by an exceptionally strong team with experience in the areas of nanophotonics, deep learning, and the development of semiconductor components,” says Michael Steiner, Member of the Executive Board for Research and Development at Porsche. “We see great potential in this sensor technology that paves the way for the next generation of driver assistance systems and autonomous driving functions. SWIR can be a key element: it offers enhanced safety at a competitive price.”

Avi Bakal, CEO and Co-founder of TriEye, commented: “Our mission is to save lives and reduce risks of accidents in all weather and lighting conditions. The expansion of our Series A round and the addition of Porsche as a strategic investor further proves that SWIR is a critical component in the necessary sensor fusion solution to enable safer and better ADAS and AV.”

TriEye is expected to exhibit at the IAA Conference in Frankfurt from September 11^th-13^th, as well as the AutoSens conference, due to take place on September 17^th-19^th in Brussels.

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Intel ships 10nm Agilex FPGAs for networking, 5G and data analytics

Congatec introduces rugged data processing engines for oil and gas

“World’s largest chip” has more compute cores for data access

Porsche invests in Israeli startup TriEye to increase road visibility and safety

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