Sector News

Entry barriers for ultra-wideband (UWB) IP in mobile, automotive, consumer and IoT applications are lowered with the RivieraWaves UWB IP claims CEVA. It can be combined with Bluetooth-UWB IP to target new use cases using both standards in emerging high-volume applications, says the company.

The RivieraWaves UWB platform IP delivers secure, centimeter-level accuracy and robust location information through time-of-flight (ToF) ranging and angle-of-arrival (AoA) processing. The MAC and PHY IP complies with the IEEE 802.15.4z standard to support enhanced ranging and security based on IEEE 802.15.4z HRP in accordance with the FiRa Consortium requirements

It is suitable for a range of low power applications and products such as tags for pinpoint asset finding, secure digital key functionality for door locks, real-time location services (RTLS) and payment systems.

Aimed at lowering the entry barrier and accelerating time-to-market for semiconductor and IoT companies looking to develop UWB-enabled devices, the RivieraWaves UWB platform IP consists of a power-optimised hardware PHY and a flexible, low latency hardware and software MAC layer. The MAC layer software can be implemented on the CEVA-BX1 DSP when deployed in combination with other connectivity workloads or modes such as direction finding, localisation or radar, or as a standalone UWB MAC on commercial Arm and RISC-V MCUs.

A flexible radio interface enables the IP to be deployed with customers’ own RF technology or with CEVA partners’ RF IP.

The RivieraWaves UWB is available for licensing now.

CEVA licenses wireless connectivity and smart sensing technologies for a smarter, safer, connected world. It provides digital signal processors (DSPs), AI engines, wireless platforms, cryptography cores and complementary software for sensor fusion, image enhancement, computer vision, voice input and artificial intelligence. The company also offers Intrinsix turnkey chip design services, helping customers address complex and time-critical IC design projects. Its technologies and chip design skills are used by semiconductor, system companies and OEMs to create power-efficient, intelligent, secure and connected devices for the mobile, consumer, automotive, robotics, industrial, aerospace and defence markets and the IoT.

https://www.ceva-dsp.com

The Vivado ML Editions deliver compile time that is five times faster than current Vivado HLx Editions. It also improves “breakthrough quality of results (QoR) improvements” of, on average, 10 per cent on complex designs, says Xilinx.

Vivado ML Editions also has team-based design flows, for significant design time and cost savings.

Vivado ML Editions accelerate design closure with ML-based logic optimisation, delay estimation and intelligent design runs, which automates strategies to reduce timing closure iterations.

According to Robert Atkinson, principal hardware engineer, National Instruments: “By offering a push-button method for aggressively improving timing results, [Vivado ML Editions] generates QoR suggestions that bring maximum impact and deliver expert quality results with a reduction in user analysis – especially for tough to close designs.”

Xilinx is also introducing the concept of an Abstract Shell, which allows users to define multiple modules within the system to be compiled incrementally and in parallel. This enables an average compile time reduction of five to 17 times, compared to traditional full system compilation, claims Xilinx. Abstract Shell also helps protect a customer’s IP by hiding the design details outside of the modules, critical for applications like FPGA-as-a-Service and value-added system integrators.

Vivado ML Editions also improves collaborative design with Vivado IP Integrator, which enables modular design using the new “block design container” feature. This capability promotes a team-based design methodology and allows a team to divide a project for multi-site, simultaneous co-operation.

Adaptability features like Dynamic Function eXchange (DFX) enable more efficient use of silicon resources by loading custom hardware accelerators, dynamically at runtime over-the-air. DFX can load design modules in a few milliseconds, which opens up new use cases such as a car swapping different vision algorithms during processing of a frame, or a genomic analysis swapping different algorithms in real-time as it sequences DNA.

Vivado ML Editions is available now in a Standard Edition at no charge and an Enterprise Edition starting at $2,995 MSRP.

http://www.xilinx.com/vivado-ml

To protect 5G networks and other critical timing infrastructure from global positioning system (GPS) signal jamming and spoofing, Microchip has integrated its BlueSky GNSS Firewall with its TimePitra 11 synchronisation monitoring and management platform. In addition to synchronisation, the combination provides single-console visibility across the entire timing architecture.

5G wireless infrastructure has more complex, higher-density synchronisation needs than earlier networks and is highly dependent on the integrity of “live-sky” timing signals from the global navigation satellite system (GNSS), explains Microchip.

The company’s TimePictra system improves overall situational awareness by managing network timing synchronisation, explains the company. The GNSS firewall that improves a network’s resilience through real-time GPS threat detection and mitigation. The scalable solution can be used by mobile operators who can use TimePictra to monitor GNSS-based source clocks along with secure network-based timing distribution solutions to deploy a resilient timing architecture for their transition to 5G.

In addition to requiring precise timing from GNSS sources, critical infrastructure operators need accurate timing to be distributed across their networks so they can ensure reliable performance and service delivery. TimePictra provides full control and monitoring for resilient timing architectures created with Microchip’s broad product portfolio including its TimeProvider 4100 grandmasters for 5G network synchronisation. It also monitors the health and performance of these networks’ distributed Precision Time Protocol (PTP) client clocks. Integrating BlueSky GNSS Firewall management into the TimePictra console view now gives operators a unified picture of the entire timing architecture and all timing sources.

Beyond supporting 5G deployments, TimePictra enables aviation, railway and maritime ports with a regional, national or global view of GNSS reception. TimePictra combined with BlueSky GNSS firewalls monitor key GNSS observables to detect live sky signal anomalies and deliver early alerts. This allows operators to follow alternate procedures that do not rely on GNSS. These capabilities are increasingly important where public safety is dependent on the position and navigation for daily operations.

Microchip’s TimePictra timing infrastructure management system with its Blue Sky GNSS Firewall is available today.

http://www.microchip.com