Sector News

Computer on Modules (CoMs) specifically designed for industrial-grade edge appliances have been announced by congatec.

According to Martin Danzer, congatec’s director of product marketing, the modules are qualified for applications exposed to extreme shock and vibrations. All provide the opportunity to deploy TSN (time sensitive networking) -capable real-time connected over the air (OTA) services and device2x communication. There are also  virtual machine implementations available, he adds, for enabling different tasks and domains on a single device. Target applications range from high-end edge servers to low power client platforms, confirmed Danzer.

Two module families are based on the COM-HPC specification. The conga-HPC/cTLU and conga-HPC/cTLH COM-HPC Client modules are based on the 11th Gen Intel Core vPro, Intel Xeon W-11000E and Intel Celeron processors. They are intended for demanding IoT gateway and edge computing applications requiring high bandwidth with up to 20 PCIe Gen 4 lanes. 

A congatec starter set is available for both module families. The starter set includes the conga-HPC/EVAL-Client carrier board, which is based on the ATX form factor. Engineers can use standard PC components for their embedded system designs. 

Another highlight for 5G platform designs is congatec’s COM Express portfolio. This now includes the COM Express Type 6 conga-TS570 modules based on the new Tiger Lake H processors. They are suitable for connected real-time IIoT gateway, edge computing and micro server workloads. For demanding transportation and mobility applications requiring high computing performance in a rugged shape, the Intel 11th Gen Core-based modules are able to operate in extreme temperature ranges of -40 to +85 degrees C. For 24/7 connected fanless embedded systems, the conga-TCV2 COM Express Compact Computer-on-Modules based on AMD Ryzen Embedded V2000 processors are another option, advises congatec. 

The modules are tailored for 5G connected and solar powered distributed process controls in smart energy grids, remote train and wayside systems, connected autonomous vehicles, and mobile outdoor equipment with limited battery capacity. The range includes Intel Atom x6000E Series, Intel Celeron and Pentium N and J Series processors on SMARC, Qseven, COM Express Compact and COM Express Mini CoM standards, as well as Pico-ITX SBCs.

For OEMs requiring 5G connected edge server level computing power, congatec’s COM Express Type 7 Server-on-Modules based on the AMD EPYC 3000 Embedded processors support up to 16 cores. Multiple cores open more options to consolidate workloads by using virtual machines on the basis of hypervisor technology from Real-Time Systems. The EPYC 3000 Embedded processors consume up to 100W TDP, so congatec has also designed cooling to ease system integration.

SMARC and Qseven platforms based on NXP i.MX 8 processor technologies for 5G includes low power SMARC and Qseven modules with machine and deep learning capabilities. They can be used in systems to see and analyse their surroundings for situational awareness, visual inspection, identification, surveillance and tracking, as well as gesture-based contactless machine operation and augmented reality. Typical examples of use will be e-charging infrastructures which require load balancing logic for various distributed charging columns and 5G connectivity for payment, services and management. 

http://www.congatec.com  

Cadence IP supporting the PCI Express (PCIe) 6.0 specification on the TSMC N5 process is now available. The Cadence IP for PCIe 6.0 consists of a DSP-based PHY and companion controller to deliver the optimised performance and throughput for applications such as hyperscale computing and 5G communications, including networking, emerging memory and storage. 

Early adopters of Cadence IP for PCIe 6.0 can access design kits now.

The 5nm PCIe 6.0 PHY test chip silicon demonstrated “excellent electrical performance” across all PCIe rates, reports the company. It was also reported that the PAM4/NRZ dual-mode transmitter delivered optimal signal integrity, symmetry and linearity with extremely low jitter. The DSP-based receiver demonstrated robust data recovery capabilities while withstanding harsh signal impairments and channel loss in excess of 35dB at 64G transactions per second. To contribute to reliability, the DSP core in the PHY provides continuous background adaptation to monitor and compensate for the signal fluctuations induced by environmental factors.

The controller IP for PCIe 6.0 is designed to provide the highest link throughput and utilisation while operating with extremely low latency. The highly scalable multi-packet processing architecture supports up to 1024-bit wide data path in x16 configuration while operating at 1GHz to achieve maximum aggregate bandwidth of 128Gbits per second. The feature-rich controller IP supports all new PCIe 6.0 features, including PAM4 signalling, forward error correction (FEC), FLIT encoding and L0p power state and retains backwards compatibility.

A PCIe 6.0 subsystem test chip was taped out on TSMC N5 in July. The subsystem test chip integrated the second generation power, performance and area (PPA)-optimised PCIe 6.0 PHY together with the PCIe 6.0 controller. The subsystem test chip enables Cadence to validate PCIe 6.0 PHY and controller functions at the system level and perform rigorous compliance and stress tests to ensure universal interoperability and reliability.

The Cadence IP for the PCIe 6.0 specification supports the company’s Intelligent System Design strategy. Cadence’s portfolio of design IP for TSMC’s advanced processes also includes 112G, 56G, die-to-die (D2D) and advanced memory IP solutions. 

http://www.cadence.com