Simplified design for FemtoClock2 lowers power budget for data centres

With jitter as low as 64fs RMS, the FemtoClock2 family is available in a small 4.0 x 4.0mm2 24- and 28-pin QFN package options from Renesas Electronics. Power consumption is just 600mW.

The sub-100fs point-of-use clock is designed for data centre, server and network infrastructure markets. The FemtoClock2 family includes low jitter clock generators and jitter attenuators in a single package, enabling cost-effective and simple clock tree implementation for next generation, high speed interconnect designs.

The best-in-class jitter enables customers to easily meet next-generation PAM4 requirements on new switch or router designs, says Renesas. The form factor makes it less than one third the size of similar products available today, says the company. Designers can place the clock source at the point of use – very close to the device receiving the clock signal – for streamlined PCB layout design, reduced cross talk, and cleaner signals. The FemtoClock2 can be configured as a DCO, clock generator, or jitter attenuator.

“PAM4 technology is enabling a major leap in data transmission rates in both communications and data centre segments resulting in stringent requirement on the clock in such systems,” said Bobby Matinpour, vice president of Renesas’ timing products, data centre business division. The small size of the FemtoClock allows it to be placed anywhere on the board at the point of use. “This greatly simplifies the design by eliminating the additive jitter associated with the extensive clock routing on the board,” said Matinpour.

Customers can combine the FemtoClock2 with Renesas’ small, single-output, high-performance oscillators, or the broader ClockMatrix portfolio of timing solutions to address challenging timing needs for their high-performance server and network infrastructure designs. FemtoClock2 also works seamlessly with systems using the recently introduced PTP Clock Manager software for IEEE 1588 support, and can be combined with Renesas’ complementary power and microcontroller offerings to create comprehensive solutions for a variety of applications, such as the IEEE 1588 Winning Combination. FemtoClock2 also serves as the downstream clock capable of delivering 100fs at the pin without disrupting the synchronization.

The RC32504A and RC22504A FemtoClocks and an evaluation board are available now.

Renesas Electronics supplies microcontrollers, analogue, power, and SoC products for automotive, industrial, infrastructure and IoT applications.

http://www.renesas.com

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Liquid-cooled models extend SiC IPMs for e-mobility

Liquid-cooled SiC MOSFET intelligent power modules (IPMs) for e-mobility have been tailored for lower switching losses or for higher power. Cissoid has added the IPMs to its three-phase SiC IPM range. It has also added a module based on a lightweight AlSiC flat baseplate that meets the demand for natural convection or forced cooling in aerospace and in dedicated industrial applications. Both integrate a three-phase SiC MOSFET module with a powerful gate driver.

The IPM technology can be rapidly adapted to new voltage, power and cooling requirements, says Cissoid. They accelerate the design of SiC-based power converters enabling high efficiency and high power density. The embedded gate driver solves multiple challenges related to fast-switching SiC transistors. For example, negative drive and active miller clamping (AMC) prevent parasitic turn-on. There is also desaturation detection and soft-shut-down (SSD) to react rapidly but safely to short-circuit events. Under-voltage lockout (UVLO) functions on gate driver and DC bus voltages monitor system operation.

Two liquid-cooled power modules are based on a pin fin baseplate and rated for 1,200V blocking voltages and for 340 to 550A maximum continuous currents. The on resistance ranges from 2.53 to 4.19mOhms, depending on current rating. The total switching energies are as low as 7.48mJ (Eon) and 7.39mJ (Eoff) at 600V/300A.

Integrating the power module and the gate driver optimises the modules for lowest switching energies by tuning the dV/dt and controlling voltage overshoots which are inherent in fast switching. The reverse bias safe operating area (RBSOA) authorises peak currents up to 600A with DC bus voltages up to 880V making the power modules perfectly safe for 800V battery applications.

The air-cooled module is designed for applications where liquid cooling is not an option, for example, aerospace electromechanical actuators and power converters. This module is rated for a blocking voltage of 1,200V and a maximum continuous current of 340A. The on resistance is equal to 3.25mOms. Turn-on and turn-off switching energies are respectively 8.42mJ and 7.05mJ at 600V and 300A. The power module is cooled down through an AlSiC flat baseplate. The module is rated for 175 degrees C junction temperature and the gate driver for 125 degrees C ambient temperature.

http://www.cissoid.com

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4K digital signage player supports multiple displays for video walls

For multi-display applications, such as video walls, digital menu boards, digital directory boards, and self-service kiosks, the DSP500 4K digital signage player is powered by the 9th/8th gen Intel Core i7/i5/i3 or Pentium processors.

It is also supported by the Intel Movidius Myriad X VPU and Intel Distribution of OpenVINO toolkit, says Axiomtek, to meet the diverse needs of computer vision and AI workloads. It also has the extended display identification data (EDID) function and three HDMI 2.0 ports that can support diverse content in retail areas.

The low power digital signage player is expandable via an internal M.2 interface for integrating the Intel Movidius Myriad X VPU and Intel Distribution of OpenVINO toolkit to develop a real-time promotion system. Data such as the gender and age of shoppers as well as using eye tracking can be used to analyse engagement with campaigns.

There is also support for Axiomtek’s exclusive Intelligent Remote Device Management (RDM) software, which provides a highly efficient and cost-effective solution with comprehensive remote management capabilities.

The DSP500 has two DDR4-2400 SO-DIMM slots for up to 32Gbyte of system memory. It also comes with one M.2 Key M 2280 for SATA and NVMe storage. To meet the requirement of diverse applications, the media player has four USB 3.1 ports, one Gigabit Ethernet ports, one device management port, one RS-232, one Line-out, one SIM card slot and four antenna openings.

Other features include one power switch, one remote switch, one clear EDID, and one VDC power input connector. It also has one M.2 Key E 2230 slot and one M.2 Key B for Wi-Fi, Bluetooth, or 4G LTE. The system operates over a temperature range of 0 to 45 degrees C.

The DSP500 runs on Windows 10 and Linux. It has been certified with CE and FCC Class A.

http://www.axiomtek.com 

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Cadence adds DSP IP cores for always-on applications

Two DSP IP cores for embedded vision and artificial intelligence (AI) have been added to Cadence Design System’s Tensilica Vision DSP family.

The Vision Q8 and Vision P1 DSPs are designed for automotive, mobile and consumer markets. The Cadence Tensilica Vision Q8 DSP delivers what is claimed to be an industry-leading 3.8T operations per second (TOPS), to double performance and memory bandwidth compared to the Tensilica Vision Q7 DSP. It also increases energy efficiency for high-end vision and imaging applications in the automotive and mobile markets. The Tensilica Vision P1 DSP is an energy-efficient DSP, optimised for always-on and smart sensor applications in the consumer market.

Based on the SIMD and VLIW architecture found in the existing Tensilica Vision DSPs, the Vision Q8 and Vision P1 DSPs feature an N-way programming model that preserves software compatibility for an easy migration from earlier Tensilica Vision DSPs with different SIMD widths. Like the rest of the Tensilica Vision DSP family, the Vision Q8 and Vision P1 DSPs support Tensilica Instruction Extension (TIE) language, allowing customers to customise the instruction set. Both DSPs also support Xtensa Neural Network Compiler (XNNC) and the Android Neural Networks API (NNAPI) for neural network support. In addition, they support more than 1,700 OpenCV-based vision library functions, OpenCL and the Halide compiler for computer vision and imaging applications. Both cores are automotive-ready with ASIL B hardware random faults and ASIL D systematic fault certification.

The seventh-generation Tensilica Vision Q8 DSP is optimised for mobile and multi-camera automotive applications. The single core simplifies system design, reducing power by up to 20 per cent, claims Cadence while an up to four-fold improvement in performance for non-convolution layers addresses the AI workload.

The Tensilica Vision P1 DSP is optimised for always-on applications including smart sensors, AR/VR glasses and IoT/smart home devices. The 128-bit SIMD architecture delivers 400G operations per second (GOPS) and offers one third the power and area, compared to the Vision P6 DSP, yet with 20 per cent higher frequency, says Cadence. The architecture is optimised for small memory footprint and operation in low power mode.

The Tensilica Vision Q8 and Vision P1 DSPs support Cadence’s Intelligent System Design strategy. The Tensilica Vision Q8 DSP is available now, while the Tensilica Vision P1 DSP is expected to be available for general release in the second quarter of 2021.

http://www.cadence.com

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