IoT

Nvidia unveils Isacc ROS GEMS with AI perception

Fri, Oct 22, 2021

At the robotics event, ROS World 2021, Nvidia unveiled Isaac ROS GEMS, graphic processing unit (GPU) programming examples. They provide packages that include image processing and computer vision, including deep neural network (DNN) -based algorithms that are optimised for Nvidia GPUs and Jetson.

As autonomous machines move around their environments, they must keep track of where they are using visual odometry which estimates where a camera is relative to its starting position. The Isaac ROS GEM for stereo visual odometry provides this functionality to ROS developers. According to Nvidia, this GEM offers the best accuracy for a real-time stereo camera visual odometry solution. In addition to being highly accurate, this GPU-accelerated package runs extremely fast. It is now possible to run SLAM on HD resolution (1280 x 720) in real-time (more than 60 frames per second) on an Nvidia Jetson AGX Xavier.

Developers can use any of Nvidia’s inference models available via Nvidia’s website or provide their own DNN with DNN Inference GEM. Pre-trained models or optimisations of developers’ own models can be tuned via Nvidia’s TAO toolkit.

After optimisation, TensorRT or Triton, Nvidia’s inference server, deploy these packages. Optimal inference performance will be achieved with the nodes leveraging the inference software development kit, TensorRT, advises Nvidia. If TensorRT does not support the desired DNN model, then Nvidia Triton should be used to deploy the model, says the company.

The GEM includes native support for U-Net and DOPE. The U-Net package, based on TensorRT, can be used for generating semantic segmentation masks from images; the DOPE package can be used for 3D pose estimation for all detected objects.

According to Nvidia, this tool is the fastest way to incorporate performant artificial intelligence (AI) inference into a ROS application.

The GA release of Isaac Sim, which will be available in November 2021, with improvements in the user interface, performance and useful building blocks to improve simulations which are built faster. There are also planned to be an improved ROS bridge and more ROS samples.

Nvidia has a virtual booth at ROS World 21, with technical presentations on Isaac.

http://www.nvidia.com

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Secora Pay on 40nm process offers new applets contactless payments

Thu, Oct 21, 2021

Contactless payment has been gaining in popularity and Infineon says its Secora Pay portfolio on 40 nm technology addresses many of the new payment card and devices. It uses the company’s Solid Flash chip and offers new applets and customised value-added products for standard payment cards (Secora Pay S) as well as multi-application cards (Secora Pay X) and components to turn any device into a payment device (Secora Pay W).

The product portfolio also provides applets of global (Visa, MasterCard, Discover, and American Express) and domestic networks. It offers state-of-the-art contactless and personalization performance, allowing MasterCard contactless transactions of 200ms.

Secora Pay options on 40 nm technology offer backward compatibility to existing Secora Pay products in terms of card production antenna designs, personalisation and product certification. The family uses a security controller including certified software integrated in coil on module (CoM) chip modules and fine-tuned inlays for seamless card production.

Infineon uses inductive coupling technology and wire embedded card antennas for the CoM system which is claimed to offer high flexibility in card designs. It can be integrated into environmentally friendly cards from recycled and ocean-bound plastic or wood, high performance dual interface metal or LED cards, says Infineon.

According to Infineon, Secora Pay products support the highest throughput in card production with minimum consumable material for manufacturing highly robust dual interface cards. As well as saving resources, new value added services based on Secora Pay’s NFC tag functionality are offered, allowing additional use cases like initial card activation.

The pre-certified Secora Pay W with SPA2.1, a small antenna on 35 mm film tape, addresses the growing demand for payment accessories and new payment form factors. In combination with payment and tokenisation services provided by partners, Infineon explains that it allows the easy integration of payment functionality into end-customer applications, for convenient contactless payment functionalities for wearables like wristbands as well as key fobs or other form factors.

Product versions supporting the latest Visa and MasterCard applications are available now. Additionally, applets supporting American Express, Discover and others will become available in Q1/2022.

http://www.infineon.com

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Microchip serves ISO 26262 functional safety packages for MCUs

Thu, Oct 21, 2021

To simplify the design of ASIL B and ASIL C safety applications using dsPIC, PIC18 and AVR microcontrollers, Microchip offers certified functional safety packages.

The certified functional safety packages enable automotive engineers to develop products as per the ISO 26262 functional safety standard. Microchip is releasing ISO 26262 functional safety packages for dsPIC33C digital signal controllers (DSCs), PIC18 and AVR microcontrollers (MCUs) to accelerate the development of safety-critical designs targeting ASIL B and ASIL C safety level and certification efforts.

The functional safety ecosystem for dsPIC33C DSCs includes AEC Q100 Grade 0-qualified functional safety ready dsPIC33C DSCs with dedicated hardware safety features. There are also SGS TÜV Saar-certified ASIL B-ready failure modes, an effects and diagnostic analysis (FMEDA) report and functional safety manual (FSM).

Designers can also access TÜV Rheinland-certified functional safety diagnostic libraries for designs targeting up to ASIL C and a functional safety reference application, showing the steps required to develop compliant designs, and the collateral that must be generated for (ASIL B or ASIL C) compliance

There are also various functional safety analysis reports and certification reports to assist compliance and certification.

For PIC18 and AVR MCUs, the functional safety ecosystem includes AEC Q100 Grade 1-qualified functional safety ready PIC18-Q84 MCUs with CAN FD and AVR DA MCUs with LIN interfaces and both with hardware support for capacitive touch sensors.

There is also the SGS TÜV Saar-certified ASIL B ready FMEDA report and FSM. In addition to functional safety diagnostic libraries, there are also ASIL B-ready certificates and certification reports.

Whether an engineer is new to ISO 26262 functional safety or a seasoned expert, Microchip says it is able to help them meet functional safety requirements and certify designs while minimising cost, risk and development time.

The functional safety packages, together with development tools (complete with the safety documents) allow engineers to develop compliant systems.

Microchip is offering three ISO 26262 functional safety packages to help customers with different levels of expertise and in different stages of their evaluation and design cycles.

The first is the functional safety basic package which offers basic resources like the ASIL B-ready certified FMEDA and safety manual to begin the evaluation of target functional safety levels and the design of safety-critical automotive applications.

Next is the functional safety starter package which offers ASIL B-ready certified FMEDA and safety manual, a reference application and ASIL C-compliant diagnostic libraries that help designers understand the ISO 26262-compliant development process and the reports that must be generated for compliance.

Thirdly, the functional safety full package is for beginners and seasoned experts to simplify the design and certification of safety-critical automotive applications. In addition to the offerings of the starter package, it includes certified diagnostic libraries with source code and the associated safety analysis reports for designs targeting up to ASIL C.

In addition to the functional safety packages, Microchip offers a TÜV SÜD-certified design tool package for its MPLAB development tools ecosystem. This includes a TÜV SÜD-certified MPLAB XC functional safety compiler with the TÜV SÜD certificate, a functional safety manual for the compiler along with safety plans and complete tools classification and qualification reports for the compiler, MPLAB X integrated development environment (IDE), MPLAB Code Coverage and all MPLAB development ecosystem programs. Microchip also offers functional safety-ready CAN FD and LIN transceivers and other companion devices, including voltage supervisor devices, which can be used with the functional safety ready DSCs and MCUs in a range of automotive applications.

The ISO 26262 functional safety ready dsPIC33C DSCs, and PIC18 and AVR MCUs are supported by the TÜV SÜD-certified MPLAB XC16 and MPLAB XC8 functional safety compilers (SW006022-FS and SW006021-FS), the MPLAB Code Coverage tool (SW006026-COV),  MPLAB X IDE, MPLAB development ecosystem debugger/programmers and the safety documentation package to make the tool qualification effort easier.

http://www.microchip.com

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Toshiba announces 20 M4N Arm Cortex-M4 microcontrollers

Wed, Oct 20, 2021

For industrial equipment requiring Ethernet and CAN control, the M4N group of Arm Cortex-M4 microcontrollers are manufactured on a 40nm process by Toshiba Electronics Europe.

They enhance the TXZ+ family and include an Arm Cortex-M4 core with floating point unit (FPU), running at speeds up to 200MHz. There is also an integrated 2Mbyte code flash and 32kbyte data flash memory with 100k write cycle endurance. The microcontrollers also offer a range of interfacing and communication options such as Ethernet, CAN and USB 2.0 FS OTG with integrated PHY.

The M4N group microcontrollers are suited to office equipment, building and factory automation applications, as well as being used in industrial networking and information management devices which are used in IoT-based home appliances, such as home security and smart meters.

They have enhanced communication functions integrated including a serial memory interface that also supports quad/octal SPI, audio interface (I2S) and external bus interface. There are also UART, FUART, TSPI and I2C interfaces supported by a built-in three-unit direct memory access controller (DMAC). The devices can allocate independent DMA and RAM for each peripheral circuit. A bus matrix circuit configuration allows the bus master to efficiently transfer data. This allows the M4N group devices to enable an Ethernet controller, CAN, and USB controller to be processed independently in parallel at the same time.

The devices support a variety of sensing applications with a high-speed, precision 12-bit analogue to digital converter (ADC) that allows individual sample and hold times to be set for each of the 24 ADC input channels. A dual-channel 8-bit digital-to-analogue converter (DAC) and a range of motor control functions are also included.

Self-diagnosis functions for ROM, RAM, ADC and clock help customers to achieve IEC60730 Class B functional safety certification, advises Toshiba.

Full documentation, sample software (with actual usage examples), and driver software for each peripheral are available for download on Toshiba’s website. Evaluations boards and development environments are also provided in cooperation with Arm ecosystem partners.

The M4N devices are available in a selection of fine-pitch LQFP and VFBGA packages.

https://toshiba.semicon-storage.com/eu

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