Embedded

The latest open specification for high performance compute modules will be under review by members of the PICMG, a consortium for the development of open embedded computing specifications.

COM-HPC is the soon-to-be-released PICMG standard for high-performance computer-on-modules (COMs). COM-HPC defines five module sizes to deliver edge server performance for small, rugged data centres. The new specification will complement COM Express, which is expected to play a crucial role in the COM marketplace “for many years”.

PICMG developed the COM-HPC specification to address emerging requirements in the embedded and edge computing market. These have seen trends, including the substantial data growth and processing requirements of broadband and 5G as well as edge analytic including AI and situational awareness applications come to the fore. IoT devices, sensors, and actuators produce large amounts of data that require pre-processing at the edge for improved data processing efficiency and end to end security. Autonomous vehicles, smart factories, smart retail, medical robotics are among many applications that will benefit from increased edge server and edge client class processors processor modules or COMs available in standard modules that existing standards cannot meet.

The COM-HPC specification is based on two 400-pin, BGA mount, high-performance connectors and a system management interface. It is not limited to x86 processors and can be used with RISC processors, FPGAs and general purpose GPUs.

The COM-HPC client modules have up to 48 + 1 PCI Express Gen4/5 lanes, up to four USB4 ports and up to four video interfaces and one or two 25Gbit Ethernet interfaces.

Module sizes are 95 x 120mm (Size A), 120 x 120mm (Size B) and 160 x 120mm (Size C).

The COM-HPC server modules are characterised by up to 64 + 1 PCI Express Gen4/5 lanes, one or two USB4 ports, up to four graphic interfaces or are headless. There are up to eight 25Gbit Ethernet interfaces.

Module sizes are 160 x 160mm and 200 x 160mm (Sizes D and E respectively).

Founded in 1994, PICMG is a not-for-profit 501(c) consortium of companies and organisations that collaboratively develop open standards for high performance industrial, Industrial IoT, military and aerospace, telecommunications, test and measurement, medical, and general-purpose embedded computing applications. There are over 130 member companies that specialise in a wide range of technical disciplines, including mechanical and thermal design, single board computer design, high-speed signalling design and analysis, networking expertise, backplane, and packaging design, power management, high availability software and comprehensive system management.

Key standards families developed by PICMG include COM Express, CompactPCI, CompactPCI Serial, AdvancedTCA, MicroTCA, AdvancedMC, COM Express, SHB Express, MicroSAM, and HPM (Hardware Platform Management).

https://www.picmg.org

Credit card sized embedded computer modules have a new footprint that reduces the size of a computer on module (COM) to a postage stamp. Technical consortium, SGET, has announced release 1.0 of the Open Standard Module (OSM) COM standard. OSM defines one of the first standards for directly solderable and scalable embedded computer modules.

The new specification aims to standardise the footprint and interface set of low-power application processors based on MCU32, Arm and x86 architectures across different sockets, manufacturers and architectures. Target applications of the new module standard include IoT-connected embedded, IoT, and edge systems that run open-source operating systems and are used in harsh industrial environments.

“OSM modules give ODMs and OEMs a miniature form factor with high scalability” explained Martin Unverdorben, chairman of the SGET STD.05 Standard Development Team. The modules are application-ready and supplied with all necessary software drivers and board support packages. The specification is open source, both in terms of the hardware and software, he added.

Like all CoM standards, OSMs simplify and accelerate the design-in of processors. At the same time, applications become processor-agnostic, which makes them scalable and future-proof, says SGET. They also protect NRE investments and extend the long-term availability, to increase RoI and sustainability of embedded systems. The OSM specification offers an extra level of ruggedness due to the BGA design and automated surface mount technology (SMT), which can further reduce production costs in series production, advises SGET.

OSMs are also published and licensed under Creative Commons Plus (CC+) dual license. This allows an open licensing model, such as the Creative Commons Attribution-ShareAlike license (CC B-SA 4.0) for a defined set of materials, components and software, and a commercial license for everything not included in this set. This ensures that development data, such as block diagrams, libraries and BOMs resulting from the development of OSMs, will be publicly available. It is also possible to license the IP of a carrier board design commercially without violating the open source idea.

The new OSM specification expands the portfolio of SGET module specifications with solderable BGA mini modules that are “significantly smaller” than previously available modules. The largest OSM measures 45 x 45mm, making it 28 per cent smaller than the µQseven module (40 x 70mm) and 51 per cent smaller than SMARC (82 x 50mm).

Other sizes are OSM Size-0 (30 x 15mm) with 188 BGA pins, OSM Size-S (30 x 30mm) with 332 pins, OSM Size-M (30 x 45mm) and 476 pins and Size-L (45 x 45mm) with 662 BGA pins. SMARC, by comparison, specifies 314 pins and Qseven 230. The BGA design makes it possible to implement significantly more interfaces on a smaller footprint, points out SGET, both in terms of miniaturisation and the increasing complexity of requirements.

The interfaces vary in type and design depending on the size of the OSM modules. Modules from Size-S upwards offer video interfaces for up to one RGB and four-channel DSI. Size-M modules can additionally support two eDP/eDP++, and Size-L adds an LVDS interface for graphics.

The OSM specification provisions up to five Ethernet for system-to-system communication. In addition, all modules have what is called a communication area, providing 18 pins for antenna signals for wireless communication or the integration of field buses. There are four USB 2.0 or two USB 3.0 (only in Size-L), up to two CAN, and four UART. Flash storage media can be connected via UFS. Up to 19 pins are available for manufacturer-specific signals. There are 39 general purpose I/Os, SPI, I2C, I2S, SDIO and two analogue inputs. Up to 58 pins are reserved for future purposes.

https://sget.org

Three 64-bit RISC-V application processor cores have been released by customisable RISC-V processor IP specialist, Codasip. The A70XP provides support for RISC-V P extensions, the A70X‑MP and A70XP‑MP enable the creation of symmetric multi-processor (SMP) systems.

The RISC-V P extension consists of 331 instructions which can be divided into groups. The A70XP includes a single instruction, multiple data (SIMD) unit which executes P extension instructions with single cycle latency. Multi-cycle instructions are pipelined to allow one to be executed every clock cycle. The core can be used for audio encoding/decoding, sensor fusion, computer vision and edge artificial intelligence/machine learning (AI/ML) applications.

The A70X-MP and A70XP-MP cores add multi-core features to the Codasip application processor family, supporting clusters of up to four cores in an SMP configuration. Codasip provides configurable L1 and L2 caches with a scalable microarchitecture. All three application processors use an AXI external interface (Advanced eXtensible Interface, part of the Arm Advanced Microcontroller Bus Architecture 3 and 4 specifications) and support Linux.

The Application RISC-V processors (denoted by product names beginning with A) are based on the same microarchitecture as the A70X (Codasip Bk7). All the Application cores are 64-bit and feature a floating point unit and Atomic instructions. They also support machine, supervisor and user privilege modes and have a memory management unit (MMU), therefore they are able to run Linux. Like other RISC-V cores by Codasip, they have been are developed using Codasip Studio allowing them to be customised to meet domain-specific requirements.

The cores have been developed as a result of combining skills at Codasip’s new design centre in France and Codasip’s main R&D centre in Brno, in the Czech Republic.

The A70X core is available today and the other three cores will be available in the first quarter of 2021.

Karel Masařík, CEO Codasip, said the company expects to introduce more new products in 2021.

Codasip offers two further processor families for the embedded domain, the small and efficient low power embedded processors and more powerful high performance embedded processors. Both of these families are based on the Codasip Bk3 and Bk5 microarchitectures.

Codasip delivers processor IP and design tools, providing IC designers with all the advantages of the RISC-V open ISA, and can customise the processor IP.

The company is a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, and is committed to open standards for embedded processors.

Codasip was formed in 2014 and is headquartered in Munich, Germany. There are offices in Europe and China, and sales representatives worldwide.

http://www.codasip.com