AI / ML-based acoustic event detection and sensor fusion alarm is battery powered

Infineon Technologies has introduced the battery-powered Smart Alarm System (SAS). It uses sensor fusion based on artificial intelligence / machine learning (AI / ML), combined with low power wake-on acoustic event detection.

The compact design is claimed to exceed the detection accuracy of acoustic-only alarm systems used today in smart buildings and homes, and other IoT applications and equal or exceed the battery life of less sophisticated systems.

The design incorporates Infineon’s high signal to noise ratio (SNR) analogue Xensiv MEMS microphone IM73A135V01, the Xensiv digital pressure sensor DPS310 and PSoC 62 microcontroller. There is also a sensor fusion software algorithm based on AI / ML that combines acoustic and pressure sensor data to differentiate between sharp sounds inside a home and distinctive audio / pressure events, such as breaking glass, a smoke alarm or a carbon monoxide alarm.

The AI / ML sensor fusion algorithm is also capable of eliminating other background sounds or background pressure events that can generate false positives due to the similarities to alarm systems, noted Infineon.

The home security alarm SAS reference design technology is available today, and the board will be available in September 2022. 

http://www.infineon.com

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Ryzen Embedded R2000 has 2x cores for IoT, says AMD

Equipped with up to two times as many cores as the previous generation of Ryzen Embedded SoC processors, the Ryzen Embedded R2000 series targets industrial and robotics systems, machine vision, the IoT and thin client equipment, said AMD.

The R2514, for example has up to 81 per cent higher CPU and graphics performance than the comparable R1000 series processor, confirmed AMD. Performance-per-watt efficiency is also optimised using Zen+ core architecture with AMD Radeon graphics for multimedia capabilities. Ryzen Embedded R2000 processors can power up to four independent displays in 4K resolution.

Embedded R2000 Series processors are scalable up to four Zen+ CPU cores with eight threads, 2Mbyte of L2 cache and 4Mbyte of shared L3 cache, allowing embedded system designers can scale performance and power efficiencies with a single processing platform, said the company. The Ryzen Embedded R2000 also supports up to 3200Mtransfer per second DDR4 dual channel memory and expanded I/O connectivity, to deliver 33 per cent higher memory bandwidth and up to two times greater I/O connectivity compared to R1000 series processors. 

The series is suitable for industrial applications like robotics and machine vision as well as thin clients and mini-PCs, which require performance, optimised power and graphics, commented the company. 

They can power up to four independent displays in 4K resolution leveraging DisplayPort 1.4, HDMI 2.0b or eDP 1.3 interfaces. They also feature peripherals and interfaces with up to 16 lanes of PCIe Gen3, two SATA 3.0 and six USB ports (USB 3.2 Gen2 and 2.0).

OS support includes Microsoft Windows 11/10, and Linux Ubuntu LTS.

 The series consists of the R2324 and R2312 SoC processors which are in production now and the R2544 andR2541 which are expected to be available in October 2022. Planned product availability extends up to 10 years, providing customers with a long-lifecycle support roadmap

http://www.amd.com 

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Tensilica DSP IP cores target radar and lidar

Two IP cores have been added to the Tensilica ConnX family of DSPs by Cadence. Intended for embedded processing in automotive, consumer and industrial markets, the ConnX 110 and ConnX 120 DSPs’ architecture is optimised for small memory footprint and low-power signal processing. The ConnX 110 and ConnX 120 DSPs share a common instruction set architecture (ISA) with the ConnX B10 and B20 DSPs preserving software compatibility for easy migration. 

The 128-bit ConnX 110 DSP and 256-bit ConnX 120 DSP feature an N-way programming model an, like the rest of the Tensilica DSP portfolio, support the Tensilica Instruction Extension (TIE) language, which allows customers to tailor the instruction set, add specialised data types, and implement tightly integrated interfaces between the DSP and external logic. 

The new DSPs are supported by a comprehensive set of complex math library functions in the NatureDSP, Eigen and Radar libraries. As with all existing ConnX DSPs, they are automotive-ready with full ISO 26262 compliance to ASIL-D with FlexLock or to ASIL-B.

The Tensilica ConnX 110 and 120 DSPs have an optimised instruction set for radar, lidar and communications applications. They also feature optional acceleration operations for linear-feedback shift, convolutional encoding, single peak search and dual peak search. The 128-bit (ConnX 110) and 256-bit (ConnX 120) SIMD are suitable for complex math operations based on eight-, 16- and 32-bit fixed-point and half-, standard- and double-precision floating-point.

The ConnX 120 additionally offers Viterbi and Turbo decoders.
NXP uses Cadence Tensilica DSP cores for its ADAS (advanced driver assistance system) product offerings, said Robert Dunnigan, director program management ADAS at NXP Semiconductors. 

Another customer, indie Semiconductor develops multiple sensor modalities “in the pursuit of the uncrashable car”. Lionel Federspiel, executive vice president of engineering for indie Semiconductor, commented: “Cadence’s Tensilica ConnX processor family in conjunction with indie’s architecture is ideally suited to implement unique design solutions with high performance, low power, and gate count optimisation. As a pure-play automotive solutions innovator, quality and reliability are essential to the success of our products.”

“Radar and communications processing trends require solutions that perform more processing in less time,” explained David Glasco, vice president of research and development for Tensilica IP at Cadence. “Automotive radar demands multi-antenna, high-resolution systems with rapid response. Similarly, 5G wireless communications requires much higher data rates and lower latencies than previous generations. The Tensilica ConnX 110 and ConnX 120 DSPs meet these demands by extending the already-efficient processing capability of the ConnX DSPs and enhancing them with even more fixed- and floating-point complex data processing capacity at low power and area.”

http://www.cadence.com

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ANS-8A64 server protects data centres to IPSec

The ANS-8A64 server series is based on an Intel Atom C3000 processor, which qualifies it for network acceleration system for software defined wide area network (SD-WAN) users, said Portwell. 

SD-WAN is used to connect a wide range of corporate networks, data centres, internet applications and cloud services, which aims to help reduce a WAN’s operating cost and improve connection flexibility, explained Portwell. More and more applications will depend on the cloud to process data, which also brings the escalating demands for network security as this data on the cloud may contain personal ID, credit card numbers and other private information. 

IPSec protocol works in the third layer of the OSI (open systems interconnection) model and supports two modes, host-to-host mode and tunnel mode, either of which can be used to build a virtual private network (VPN) to increase the security of network transmission.

The Intel Atom C3000 processor series features industry-leading performance per watt, claimed Portwell, with low thermal design power (TDP) and configurable high-speed I/O, making it suitable for networks, storage devices, IoT and scalable designs. It is also equipped with Intel QuickAssist Technology (Intel QAT). The Intel QAT engine means IPSec protocol operation, data encryption, decryption and compression can be handled independently. It saves the CPU resource for other critical workloads and eventually optimises the overall work efficiency and performance, said Portwell.  

During field tests of the data plane development kit (DPDK) and Intel QAT, the ANS-8A64 was used as IPSec gateways and the encryption and decryption performance was repeatedly tested. 

In a one-way test, packets are sent unidirectionally from server port1 to server port2, and encryption and decryption are performed by IPSec gateway1 and IPSec gateway2.

A two-way test, consists of the server port1 and server port2 sending packets at the same time, and encrypting and decrypting packets through IPSec gateway1 and IPSec gateway2.

Portwell reported that the hardware acceleration engine, Intel QAT offers a “significant system optimisation and effectively betters the overall performance in both one-way and two-way testing”. 

Portwell is an Associate member of the Intel Internet of Things Solutions Alliance, designs and manufactures a full range of IPC products (SBC, backplane, redundant power supply, rack mount and node chassis), embedded architecture solutions, DVR system platforms and communications appliances. It provides R&D and project management services to decrease customers’ time to market and reduce project risk and cost. Portwell is also an ISO 13485, ISO 9001 and ISO 14001 -certified company that deploys quality assurance through product design, verification and manufacturing cycles. 

http://www.portwell.eu 

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