SoMs are pin-compatible with Intel Agilex I- and F- FPGA SoCs

System on modules (SoMs) that support Intel Agilex FPGA SoCs have been released by iWave. The iW-RainboW-G43 and iW-RainboW-G51 Agilex SoC based SoMs are designed for data centre, networking and edge applications which can exploit the SoCs customised acceleration and connectivity characteristics.

According to iWave, they provide an improvement in performance with 40 per cent lower power consumption while delivering two times the fabric performance per Watt. The SoCs integrate the Arm Cortex A53 Core application processor.

The SoMs are available in a 120 x 90mm form factor and are claimed to be the first SoMs to be pin compatible for the majority of the F-Series and the I-Series. 

The Agilex SoM has up to 2.7M programmable logic elements for processing large amounts of, or complex, data algorithms. The SoM supports primary interface and components, such as Gigabit Ethernet, USB2.0 port, JTAG, UART, onboard DDR4 and eMMC flash for storage, high-speed transceivers.

Complementing the Agilex SoC on-chip resources, the SoM provides up to 64 FGT transceiver channels (up to 32G NRZ / 58G PAM4), up to eight FHT transceiver channels (up to 58G NRZ / 116G PAM4), on SoM PTP and SyncE network synchronisers, SmartVID to adjust voltage as per the temperature and performance requirements and up to 138 LVDS/276 SE I/Os.

To enable quick prototyping and speed up development, iWave supports customers by providing reference designs in the form of development kits and software packages. 

http://www.iwavesystems.com 

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Andes Technology teams up with Green Hills Software for automotive RISC-V 

RISC-V CPU IP vendor, Andes Technology, and Green Hills Software will collaborate to develop an integrated, secure hardware-software platform for automotive applications.

Andes Technology’s ASIL-certified AndesCore 25-Series RISC-V processor family will be integrated with Green Hills’ safety-certified µ-velOSity real time operating system (RTOS), the ASIL-certified MULTI development environment with advanced system-level debugging and analysis tools and C/C++ optimising compilers, along with the Green Hills probe for JTAG and trace target connections.

The combined hardware and software platform is designed for SoC companies and end customers to create market-leading 32bit / 64bit RISC-V-based SoCs targeting critical functions requiring ISO 26262 ASIL B to ASIL D. The offering will be used for vehicle electronics requiring compact and cost-sensitive SoCs that are still capable of ASIL certification, confirmed Green Hills Software.

The CPU IP cores are based on AndesStar V5 architecture incorporating RISC-V technology. Its five-stage pipeline is optimised for high operating frequency and high performance, with a small gate count. The 25-Series supports optional single- and double-precision floating point instructions. It also offers branch prediction for efficient branch execution, instruction and data caches, local memories for low-latency accesses, and ECC for L1 memory soft error protection.

Through design guidance and training, Green Hills Software’s services teams help customers achieve their own tailored levels of safety, security, and performance, with the highest developer productivity.
Andes Technology claims to be the first RISC-V processor IP vendor to receive ASIL D process certification for both hardware (ISO 26262-5) and software (ISO 26262-6). The functional safety-enabled Andes Technology and Green Hills Software offering is expected to be available for general licensing by the second half of 2022.

“AndesCore RISC-V processor IP with safety enhancement has already been adopted by several early customers,” said Dr Charlie Su, Andes technology president and CTO. “The . . . partnership with Green Hills Software enables us to further offer comprehensive and robust development support for our customers. We welcome the benefits that Green Hills Software’s mature functional safety solutions bring to the RISC-V community to speed up the adoption of RISC-V safety-related applications,” he added.

Expanding the Green Hills’ portfolio to include the latest advanced safety-certified RISC-V AndesCore IP in a combined hardware-software solution means “SoC providers using the AndesCore 25-Series family can immediately start developing their next generation vehicle ECUs with the highest performing, lowest power offerings, while reducing their customers’ time to market and development costs by offering integrated and optimised production-proven solutions,” said Dan Mender, vice president, business development, Green Hills Software.

http://www.ghs.com

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Aitech release three 3U VPX cybersecurity-enabled SOSA aligned SBCs 

Rugged board provider, Aitech Systems offers three configurations of 3U VPX cybersecurity-enabled SBCs (single board computers) aligned to The Open Group Sensor Open Systems Architecture (SOSA) technical standard. 

The U-C8500, U-C8501 and U-C8502 use powerful Intel TigerLake SoCs with integrated general purpose graphics processor units (GPUs) to optimise SWaP-C for interconnectivity in military, aerospace and space applications.

The U-C850x series of SBCs combine modern data processing acceleration, CPU, iGPU and FPGA. It includes a high-performance CPU SoC with an internal GPU, combined with optional integrated large FPGA. As a result, the SBCs are suitable for rugged military and aerospace data-intensive applications, including AI and machine learning, while minimising SWaP-C and without sacrificing performance, said Aitech Systems.

The U-C850x series fully supports AiSecure, Aitech’s proprietary cybersecurity framework that increases survivability and level of confidence by detecting and preventing unexpected attacks. The inherent security features enable both firmware and data protection as well as prevents reverse engineering and tampering with system integrity, while allowing secure transmission and storage of sensitive data.

The U-C850x series of rugged 3U VPX SBCs features a multi-core Intel Architecture CPU processor, strong general purpose GPU AI processing and advanced cybersecurity protection. The Intel 11th generation TigerLake UP3 (TGL-UP3) SoC with four cores/ eight threads and a GPU with up to 96 execution units enables 12W, 15W and 28W TDP (thermal design performance) options. 

The U-C8500 is a four PCIe Gen3/4 data plane with an XMC slot, the U-C8501 is a four PCIe Gen3 Data Plane, four PCIe Gen4 expansion plane with an XMC slot and the U-C8502 is a four PCIe Gen3 data plane, four PCIe Gen4 expansion plane with integrated Xilinx MPSoC FPGA. 

According to Aitech, the U-C850x series has highly integrated functionality and excellent SWaP-C for use in harsh military and aerospace applications that need to reliably process significant amounts of data, for example, unmanned aerial vehicles and unmanned ground vehicles (UAV/UGV), mission computers and digital signal and image processing as well as signal intelligence (SIGINT) and electronic warfare (EW).

The boards feature support for up to 64Gbyte LPDDR4X RAM to provide the performance required for graphics and AI/ML applications using the integrated general purpose GPU as well as PCIe Gen4 support for optimised interconnect to other boards in the system.

http://www.aitechsystems.com

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NeuralVDB reduces memory footprint and adds AI 

Building on the development of OpenVDB, the open source C++ library for volumetric data, Nvidia has announced NeuralVDB, which brings the power of AI to OpenVDB.

It reduces memory footprint by up to 100 times which allows professionals working in scientific computing and visualisation, medical imaging, rocket science and visual effects to interact with extremely large and complex datasets in real time.

In the last decade, explained Ken Museth, senior director of simulation technology at Nvidia, OpenVDB has moved out of the visual effects industry and into industrial design and scientific use cases where sparse volumetric data is prevalent.

NeuralVDB joins Nvidia’s NanoVDB which was introduced last year, adding GPU support to OpenVDB. This accelerated performance and opened the door to real-time simulation and rendering, said Museth.

NeuralVDB builds on this GPU acceleration by adding machine learning to introduce compact neural representations that “dramatically reduce” its memory footprint. As a result, 3D data can be represented at even higher resolution and at a much larger scale than OpenVDB. Users can therefore handle massive volumetric datasets on devices like individual workstations and even laptops, said Nvidia.

NeuralVDB compresses a volume’s memory footprint up to 100x compared to NanoVDB which allows users to transmit and share large, complex volumetric datasets more efficiently.

To accelerate training up to a factor of two, NeuralVDB allows the weights of a frame to be used for the subsequent one. NeuralVDB also enables users to achieve temporal coherency, or smooth encoding, by using the network results from the previous frame.

This combination reduces memory requirements, accelerates training and enables temporal coherency offering new possibilities for scientific and industrial use cases, including massive, complex volume datasets for AI-enabled medical imaging and large scale digital twin simulations.

http://www.nvidia.com

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