Embedded

The latest release of Segger’s Embedded Studio for Arm is supplied with STOP (stack overflow prevention) designed to reliably prevent stack overflows. With STOP ena-bled, the compiler adds a call to a stack limit-check routine wherever necessary, before adjusting the stack pointer.

The STOP option for the Segger Compiler can be easily switched on, without any change to application code. This way, all stack overflows are prevented. If a stack overflow has been prevented, the system can enter a safe state and recover.

STOP has a surprisingly low impact on size and speed. It adds only about two to five per cent to code size and execution time, which typically does not have a significant impact on the performance of the system.

A stack overflow can cause all kinds of failures in an embedded system, from hard-to-detect, seemingly random miscomputations to severe malfunctions or even crashes.

STOP protects all stacks in the system. It protects the process stack, as well as the  main stack used for interrupts. It can be used with any real time operating system (RTOS), provided the RTOS updates the stack-limit variable on a context switch.

The technology is currently available for Thumb-2 architectures such as Cortex-M4, Cortex-M7, Cortex-A9, and Cortex-A15.

On ARMv7M architectures, STOP is ready to use in Embedded Studio with a single project option switch.

The STOP feature is recommended for all, but deemed essential for safety critical applications, said Segger, which believes it is the only company offering such technology today. It can be used by software engineers, students or hobbyists. “It takes less than 15 minutes, is easy and hassle-free,” said Rolf Segger, the company’s founder.  It is also cost-free for evaluation, education, and non-commercial purposes.

Embedded Studio is Segger’s multi-platform IDE (integrated development environment). Characterised by its flexibility of use, it includes all the tools and features a developer needs for professional embedded C and C++ programming and development. It comes with Segger’s optimised emRun runtime and emFloat floating-point libraries, as well as Segger’s smart Linker, all of which have been developed from the ground up specifically for resource-constrained embedded systems. In combination with the Clang-based optimising C/C++ Segger compiler, extremely small yet efficient programs can be generated, putting every byte to work.

Embedded Studio is available on all platforms (Linux, macOS, and Windows) on Arm, Intel, and Apple Silicon.

http://www.segger.com

FPGA and embedded FPGA (eFPGA) IP provider, Achronix has announced that its suite of flexible FPGA IP blocks, the Achronix Network Infrastructure Code (ANIC) includes 400 Gigabit Ethernet (GbE) connectivity. ANIC IP blocks are optimised to accelerate high performance networking pipelines for Speedster 7t FPGAs and the VectorPath accelerator card.

As the demand for high speed data processing continues to grow exponentially, said Achronix, it has developed its IP to address the evolving needs of the networking industry. Integrating 400 GbE and PCIe Gen 5.0, Achronix empowers data centre operators, cloud service providers and telecommunications companies to create SmartNIC solutions which are scalable and flexible.

With 400 GbE support, the ANIC IP enables fast data transfer rates, allowing organisations to process massive amounts of data in real time. This accelerated network throughput maximises application performance and significantly reduces latency, said the company.

ANIC’s modular architecture enables customers to select SmartNIC components necessary for an application. Each optimised IP block is pre-verified with closed timing to speed design. Coupled with partial reconfiguration (the ability to dynamically change the functionality of a block within the IP design), solutions can be seamlessly modified in the field.

Customers can deploy custom IP functions, such as key value stores, intrusion prevention, de-duplication and other network applications, to provide highly parallelised, value added network solutions at 400 GbE network speeds.

Steve Mensor, vice president of marketing for Achronix Semiconductor described the introduction of 400 GbE as a breakthrough which will allow customers to unlock new levels of performance and address the ever-growing demands of modern data centres and communication networks.

ANIC modular IP runs on Speedster7t AC7t1500 FPGAs and VectorPath S7t-VG6 accelerator cards offering what is claimed to be the industry’s highest performance for networking and compute acceleration applications. The Speedster7t architecture includes a 2D network on chip (2D NoC) that provides 20 Tbits per second of total bandwidth. The 2D NoC offers high speed connectivity between the FPGA fabric and the high speed interfaces including 400 GbE, PCIe Gen 5.0, GDDR6, and DDR4/5. Additionally, Speedster7t FPGAs have machine learning processors (MLPs) distributed across the FPGA fabric. Each MLP is a highly configurable, compute-intensive block, with up to 32 multipliers that support integer formats from four to 32 bits and various floating-point modes including direct support for TensorFlow’s bfloat16 format and block floating-point (BFP) format.

Achronix Semiconductor is a fabless semiconductor company based in Santa Clara, California, USA, offering FPGA-based data acceleration solutions, designed to address high- performance, compute-intensive and real time processing applications. Achronix claims to be the only supplier to have both high-performance, high-density standalone FPGAs and licensed eFPGA IP solutions.

Its portfolio includes Speedster 7t FPGA and Speedcore eFPGA IP as well as  ready-to-use VectorPath accelerator cards targeting AI, machine learning, networking and data centre applications. All Achronix products are fully supported by the Achronix tool suite which enables customers to quickly develop their own custom applications.

Achronix has sales and design teams across the US, Europe and Asia. 

http://www.achronix.com