ADLINK introduces COM-Express Type 7 module

ADLINK has announces the launch of its Express-VR7 module with up to 8 cores at 15W, 45W powered by AMD Ryzen Embedded V3000. The COM-Express Basic size Type 7 module boasts as a go-to solution for various mission-critical data processing and networking applications at 15W, 45W TDP.

“It is evident that edge networking demands have been trending towards more and more compact, fanless, power-efficient designs that can withstand normal to harsh environments, “said Lauryn Hsu, Senior Product Manager at ADLINK COM. “Blending AMD ‘Zen 3’ high-performance architecture with topnotch energy efficiency and industrial-grade reliability, Express-VR7 strikes the perfect balance between performance and power consumption in constant networking and edge systems.”

“We are excited to collaborate with ADLINK on its newest Express VR7 module powered by our AMD Ryzen™ Embedded V3000 processor,” said David Rosado, senior product marketing manager, Embedded Processors Group at AMD. “With its combination of high-performance and power efficiency, the Ryzen Embedded V3000 is a great addition to the Express VR7 module especially for developers who require a robust Computer-on-Module solution with advanced features for edge computing.”

Integrating 14x PCIe Gen4 lanes and 2x10G Ethernet interfaces that are backplane KR, copper, and fibre optic compatible, and is available with extreme temperature option (-40°C to 85°C), the ADLINK Express-VR7 module can realize wide-ranging edge networking innovations, such as edge networking equipment, 5G infrastructure at the edge, video storage analytics, intelligent surveillance, and industrial automation and control.

ADLINK is also working to provide I-Pi development kits based on the Express-VR7 module for out-of-the-box-ready prototyping and referencing.
https://www.adlinktech.com

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Renesas unveils the first generation of 32-bit RISC-V CPU core

Renesas has announced that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V instruction set architecture (ISA). Renesas is among the first in the industry to independently develop a CPU core for the 32-bit general-purpose RISC-V market, providing an open and flexible platform for IoT, consumer electronics, healthcare and industrial systems. The new RISC-V CPU core will complement Renesas’ existing IP portfolio of 32-bit microcontrollers (MCUs), including the proprietary RX Family and the RA Family based on the Arm Cortex-M architecture.

RISC-V is an open ISA which is quickly gaining popularity in the semiconductor industry, due to its flexibility, scalability, power efficiency and open ecosystem. While many MCU providers have recently created joint investment alliances to accelerate their development of RISC-V products, Renesas has already developed a new RISC-V core on its own. This versatile CPU can serve as a main application controller, a complementary secondary core in SoCs, on-chip subsystems, or even in deeply embedded ASSPs. This positions Renesas as a leader in the emerging RISC-V market, following previous introductions of its 32-bit voice-control and motor-control ASSP devices, as well as the RZ/Five 64-bit general purpose microprocessors (MPUs), which were built on CPU cores developed by Andes Technology Corp.

“Renesas takes pride in offering embedded processing solutions for the broadest range of customers and applications,” said Daryl Khoo, Vice President of the IoT Platform Division at Renesas. “This new core extends our leadership in the RISC-V market and uniquely positions us to deliver more solutions that accommodate a diverse range of requirements.”

“We congratulate Renesas on achieving its recent milestone in 32-bit RISC-V MCU architecture development,” said Calista Redmond, CEO at RISC-V International. “This achievement exemplifies how RISC-V ecosystem partners, such as Renesas, are rapidly advancing RISC-V innovation. Our RISC-V community now spans 70 countries with more than 4,000 members, and we eagerly anticipate further innovations emerging from this dynamic, expanding market.”

The Renesas RISC-V CPU achieves an impressive 3.27 CoreMark/MHz performance, outperforming similar architectures on the market. It includes extensions to improve performance, while reducing code size.
Renesas is sampling devices based on the new core to select customers, with plans to launch its first RISC-V-based MCU and associated development tools in Q1 2024. Details of the new MCU will be published at that time. More information about RISC-V solutions is available at: renesas.com/risc-v.

https://www.renesas.com/

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Microchip unveils new standard of enhanced code security with the PIC18-Q24 family of MCUs

More and more everyday items are connected to the cloud—from cellphones and vehicles to smart thermostats and home appliances. With this rise in connectivity, the need for advanced security measures at the chip level, protecting both firmware and data, is critical. To defend against current and ever-expanding security threats, Microchip has launched the PIC18-Q24 family of MCUs.

To counter the threat of maliciously reprogramming a device in an embedded system, PIC18-Q24 MCUs introduce the programming and debugging interface disable (PDID) feature. When enabled, this enhanced code protection feature is designed to lock out access to the programming/debugging interface and block unauthorised attempts to read, modify or erase firmware.

“System security is only as strong as its weakest link. Any programmable component can be vulnerable, and it is essential to implement enhanced protection features to prevent potential hacks,” said Greg Robinson, corporate vice president of Microchip’s 8-bit MCU business unit. “The PIC18-Q24 family of MCUs from Microchip are designed with advanced security in the forefront, to help customers combat threats at the system’s foundation.”

Because many secure systems often connect and communicate with a wide variety of sensors, memory chips and processors, the PIC18-Q24 MCUs feature Multi-Voltage I/O (MVIO). This feature eliminates the need for external level shifters and allows the MCUs to interface with digital inputs or outputs at different operating voltages. In addition to reducing board complexity and Bill of Material (BOM) cost, MVIO makes PIC18-Q24 MCUs especially well-suited as system management processors, performing monitoring and telemetry for a larger processor. These seemingly routine tasks are typically most vulnerable to potential hackers as they try to gain access to embedded systems.

The PIC18-Q24 family is also enabled with the option to have an immutable bootloader for applications that want a secure way to upgrade firmware.

https://www.microchip.com

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Mini airport booth displays Terion and Secora Pay demos for high performance government IDs and payment

At Trustech, the tradeshow for innovative payment and identification solutions, Infineon will present the latest member of the Tegrion family, which accelerates future-proof ID applications. Infineon’s mini airport booth will also feature the world’s first PQC-enabled ePassport demonstrator. In addition, visitors can experience the convenience of seamless payment with Secora Pay X, which will be demonstrated in a pop-up manicure salon for fingernails suitable for contactless payment.

The Tegrion SLC26G is a security controller for demanding identity and government ID applications such as ePassports, national eID and eHealth Care systems. The security controller enables customers to quickly and easily implement their operating system and the corresponding applications. Even more, the controller offers highest levels of security, speed, performance and power efficiency that are essential for government ID applications. These require permanent security throughout the life of the documents, as well as fast transaction times, for example at border control when travel documents need to be checked electronically at an eGate. For this ultra-fast contactless communication, the Tegrion SLC26G integrates Very High Bit Rates (VHBR).

In addition, the security controller is equipped with the integrated Integrity Guard 32 security architecture, which provides highest levels of security without compromising on transaction performance. The Integrity Guard 32 digital security technology, combined with the Arm® v8-M instruction set and powerful crypto accelerators, offers highest levels of protection, high communication speed and extremely low power consumption. Based on Infineon’s 28 nm technology, the Tegrion family meets even most demanding security standards and requirements.

Infineon, Bundesdruckerei GmbH and the Fraunhofer Institute for Applied and Integrated Security (AISEC) present the world’s first demonstrator for an electronic passport that meets security requirements of the quantum computing era (Post Quantum Cryptography, PQC). The demonstrator shows a solution for contactless data transmission between the ePassport and the border control terminal. The solution is based on a quantum-resistant version of the Extended Access Control (EAC) protocol and secures biometric data during authentication. The security procedures are compatible with established structures and can also implement quantum-resistant encryption.

Biometric payment cards offer a more convenient and hygienic payment experience, as cardholders can verify their identity by simply placing a finger on the card sensor and tapping the card on the terminal. This allows to make the biometric payment process faster than standard PIN-based transactions. To further improve the performance and production efficiency of biometric payment cards, Infineon is working with Fingerprints™ to develop the complete Secora Pay Bio solution. This turnkey solution comes with a pre-certified Java Card operating system including Mastercard and Visa Bio applets for cost-effective, scalable production based on state-of-the-art card manufacturing equipment. A Secora Pay Bio demo will be shown at the Infineon booth, highlighting the key requirements for a successful biometric payment card solution, including the various enrolment options.

This year, Infineon’s partner Smart Chip Switzerland will present an innovative pop-up fingernail salon at the Infineon booth, giving the public the opportunity to test the next level of payment: Brave visitors can have a specially designed inlay with Infineon’s Secora Pay X solution placed directly on their fingernail for on-the-go payment. In addition, numerous other new wearable payment devices, including rings, bracelets, key fobs and watches, will be presented in the service area of the booth. All these devices are equipped with products from the Secora Pay or Secora Connect solution families for connected IoT devices for secured payment. Based on an enhanced NFC Secure Element design, Secora Connect enables smart wearables with payment, ticketing and other applications for both battery-less operation and battery-powered devices with the lowest possible power consumption to maximize battery life for the consumer.

As cities grow, public transport operators are faced with ever-increasing passenger numbers, especially during major events such as football matches and the Olympic Games. Combined with the need for sustainability and convenience, this is creating a rapidly growing market for digital ticketing and smart mobility. However, this requires open standards for designing secured, convenient and interoperable ticketing solutions with the necessary transparency and trust.

Infineon addresses this development with Calypso move, the first secured memory for simple contactless ticketing based on the Calypso® base specification. It enables manufacturers to meet the specific requirements of any transport company or authority and to avoid the use of magnetic strips, barcodes or proprietary tickets. A Calypso move sample card will be on display at the Infineon booth at Trustech.

https://wwww.infineon.com/trustech.

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