Components & Connectors

Commercial interconnect IP from Arteris IP, is claimed to accelerate the development of next-generation deep neural network (DNN) and machine learning systems. The FlexNoC version 4 interconnect IP and the companion AI Package. FlexNoC 4 and the AI Package (FlexNoC 4 AI) implement new technologies that ease the development of today’s most complex AI, deep neural network (DNN), and autonomous driving SoCs, explains Arteris.

Arteris IP created the new technologies in FlexNoC 4 AI based on its learning from customers, including Mobileye, which recently licensed Arteris IP FlexNoC and Ncore interconnect IP for its next-generation EyeQ systems.

Using automated topology generation for mesh, ring and torus networks, the FlexNoC 4 AI enables SoC architects to generate AI topologies automatically and also edit generated topologies to optimise each individual network router, if desired.

The FlexNoC 4 AI intelligent multicast optimises the use of on-chip and off-chip bandwidth by broadcasting data as close to network targets as possible. This allows for more efficient updates of DNN weights, image maps and other multicast data.

Another feature, source synchronous communications, helps avoid clock tree synthesis, physical placement, and timing closure problems when spanning long distances on AI chips, which can be larger than 400mm².

The VC-Link virtual channels allow long physical links to be shared in congested areas of the die while maintaining quality of service (QoS).

There is also support for HBM2 and multichannel memory and for up to 2048-bit wide data.

The FlexNoC 4 interconnect IP and the FlexNoC 4 AI Package are available immediately.

Arteris IP provides network in chip (NoC) interconnect IP to accelerate SoC semiconductor assembly for a range of applications from artificial intelligence (AI) to automobiles, mobile phones, IoT, cameras, SSD controllers, and servers. Its customer base include Samsung, Huawei, HiSilicon, Mobileye and Texas Instruments. The IP product line can help customers obtain lower power, higher performance, more efficient design reuse and faster SoC development, to lower development and production costs.

http://www.arteris.com

Intel has added the Intel Programmable Acceleration Card (PAC) with its most powerful FPGA, the Intel Stratix 10 SX FPGA. The high-bandwidth card leverages the Acceleration Stack for Intel Xeon CPU with FPGAs, allowing data centre developers to deploy FPGA-based accelerated workloads.

Following on from the earlier Intel PAC with Intel Arria 10 FPGA, the Intel PAC with Stratix 10 SX FPGA supports an ecosystem of design partners that delivers IP to accelerate a range of application workloads.

The Intel PAC with Stratix 10 SX FPGA is a larger form factor card built for inline processing and memory-intensive workloads, like streaming analytics and video transcoding. (The smaller form factor Intel PAC with Arria 10 FPGA is designed for back testing, data base acceleration and image processing workloads.)

It has been developed in response to increasing demands for big data and artificial intelligence (AI) increase, necessitating the reprogrammable technology of the FPGA to meet the processing requirements and changing workloads of data centre applications. The FPGA’s reconfigurable logic, memory and DSP blocks, mean that it can be programmed to execute any type of function with high throughput and real-time performance, making them, claims Intel, ideal for many critical enterprise and cloud applications.

The acceleration stack for Intel Xeon CPU with Intel FPGAs works with industry-leading OS, virtualisation and orchestration software partners, providing a common interface for software developers to get simplified management and access to a growing ecosystem of acceleration workloads.

The Intel PAC with Stratix 10 SX FPGA includes a production-grade FPGA interface manager (FIM) to which Intel and partner AFUs are connected. There is also an acceleration stack for Intel Xeon CPU with FPGAs, including a common set of application programming interfaces (APIs) and open-source drivers and support for native, network-attached workloads. Initial partners include Adaptive Microware and Megh Computing.

It was announced that Hewlett Packard Enterprise will be the first OEM to incorporate the Intel PAC with Stratix 10 SX FPGA along with the Intel Acceleration Stack for Intel Xeon Scalable processor with FPGAs into its server offering.

http://www.intel.com