To enable a “significant increase” in baud rate combined with at least 80GHz analogue output bandwidth, a scalable SiGe BiCMOS technology developed by Imec, can be produced in volume, “paving the way to cost-effective, high-speed optical transceivers for the Tbit era,” said the research group.
It has been designed for data-intensive applications, such as cloud services, video streaming, high-performance computing and 5G, which place demands on optical communication networks within data centres. The most performant optical links operate at speeds up to 400Gbits per second, using for example four 100Gbit per second channels. Data centre operators believe that Terabit per second optical transceivers will be needed within a few years. At the same time as the increasing demands on data centres’ optical networks, co-packaged paradigms are emerging to help optical switches manage the massive bandwidth density at input. These are also expected to reach 100Terabits per second. In these co-packaged optics, Si photonics transceivers are tightly integrated with the high-speed electronic circuits.
Increasing the capacity of the optical links despite the smaller footprints of transceivers will impact the design of photonic high-speed ICs used in transceivers, said Imec. One solutions is to increase signalling rates beyond 100Gbaud. Such rates may be beyond the capabilities of advanced CMOS nodes (for example FinFETs), leaving greater than 100Gbaud speeds to be handled by InP technologies, where their smaller wafer sizes and reduced capability to integrate more complex functionality makes scaling up these processes challenging. Imec is looking at III-V on CMOS processes, initially with the integration of novel circuit architectures in SiGe BiCMOS to achieve beyond 100Gbaud operation.
Scientists from imec-IDLab have developed a novel transmitter architecture that has key building blocks fabricated in a mainstream SiGe BiCMOS process. Imec’s Peter Ossieur, explained: “The resulting IC decodes four 30Gbaud PAM-4 (or four 60Gbits per second NRZ) streams, and simultaneously multiplexes and equalises these streams into a 120Gbaud PAM-4 signal with more than 80GHz bandwidth, 1.2Vpp voltage swing and 2200mW power consumption. Since the four-level pulse amplitude PAM-4 modulation format involves two bits per symbol (denoted as 00, 01, 10 and 11), this is the equivalent of a 240Gbit per second (single lane) transmitter, he told Electronic Design.
Within the transmitter IC, a multiplexer (MUX) combines multiple low-speed input signals from a CPU or GPU within the data centre, into a single full-rate data stream. This stream is then equalised to compensate for any bandwidth losses in the modulator and the channel. The high-speed equalised signal is then used as an input signal for the driver that subsequently feeds the optical modulator.
Rather than performing equalisation in the digital domain using a DSP, before conversion into an analogue signal, Imec has developed a transmitter IC architecture which implements an analogue signal processing variant of the DSP filter, with the integrated MUX, FFE and driver fabricated in mainstream 55nm SiGe BiCMOS.
“The work shows a doubling of the operating rate compared to FinFET solutions and closely matches the speed and power obtained in InP-based solutions”, reported Peter Ossieur.
“These building blocks will also be crucial for developing novel coherent transceiver concepts, which exploit the phase and polarisation of the optical field to further increase the bit rate,” said Ossieur.
