Sensor uses motion and bone conduction to save space and power

Headsets and hearable devices can be reduced in size and power budget using the STMicroelectronics’ motion and bone-conduction sensor, said the company. The LSM6DV16BX can deliver a longer listening experience and superior hearing in TWS (true wireless stereo) headphones and AR / VR / MR headsets.
The integrated sensors can save space inside hearable devices including sports and general-purpose earbuds. It combines a six-axis inertial measurement unit (IMU) for head tracking and activity detection with an audio accelerometer for detecting voice through bone conduction in a frequency range that exceeds 1kHz.

The LSM6DSV16BX contains ST’s Qvar charge-variation detection technology for user-interface controls such as touching and swiping.
The LSM6DSV16BX sensor embeds ST’s Sensor Fusion Low Power (SFLP) technology, specifically designed for head tracking and 3D sound, and the in-the-edge processing resources featured in ST’s third generation MEMS sensors, including finite state machine (FSM) for gesture recognition, the machine learning core (MLC) for activity recognition and voice detection, and adaptive self-configuration (ASC), which automatically optimises performance and efficiency. These help to reduce system latency while saving overall power and offloading the host processor.
The enhanced integration and edge processing save up to 70 per cent of system power consumption and 45 per cent of PCB area. In addition, the number of pin connections can be reduced by 50 per cent, saving external connections, and the package height is 14 per cent less than earlier MEMS inertial sensors from ST.
The LSM6DSV16BX comes with many software examples, available on ST MEMS GitHub FSM and MLC model zoo. These include pick-up gesture detection to automatically turn on some device’s services, in-ear and out-of-ear detection in TWS headsets and head gestures for 3D sound in headphones. To save developer time, without starting from scratch, pre-integrated application examples are available in X-Cube-MEMS1 package.
The LSM6DSV16BX is in production now, available in a 2.5 x 3.0 x 0.74mm VFLGA package.

 

http://www.st.com/

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Optical interconnect scales to AMD’s adaptive SoCs

At OFC, the optical communications and networking conference in San Diego, California (05 to 09 March), Ranovus has demonstrated a low power consumption,  800Gbits per second Ethernet interoperable link which is interoperable with AMD’s adaptive SoCs for AI / ML (artificial intelligence / machine learning) applications.

The Odin direct drive CPO 2.0 optical interconnect has 5pJ/bit energy efficiency and is claimed to be best-in-class for co-packaged, near-packaged optics and pluggable module form factors. 

The company demonstrated interoperability of the AMD Versal adaptive SoCs with the co-packaged Odin 800G direct drive optical engine and third party 800G DR8+ retimed pluggable modules. 

Ranovus’ Odin is a low latency, high density, protocol agnostic and standards-based optical engine that delivers massive optical interconnect bandwidth with industry-leading cost and power efficiency, claimed the company. Built on GlobalFoundries’ Fotonix monolithic RF / CMOS silicon photonics (SiPh) platform, Odin incorporates Ranovus’ proprietary RF CMOS, silicon photonics, laser and packaging technologies for volume manufacturing.  Odin is well suited for next-generation data centre architectures built on co-packaged optics, near-packaged optics, and pluggable OSFP / QSFP-DD / OSFP XD optical modules.

Dr Christoph Schulien, head of Systems and high speed IC R&D of Ranovus, said that the inherent versatility enables hyperscale data centre providers to drastically reduce power consumption and optimise density and cost as they deploy novel hybrid data centre architectures in response to the insatiable growth in AI / ML workloads.

Yohan Frans, vice president, engineering at AMD, said: “We are proud of our collaboration with Ranovus in demonstrating the performance and versatility of monolithic silicon photonics interconnects as data centre and 5G customers deploy highly efficient and cost-effective systems for next generation workloads.”

The interoperability between CPO and pluggable modules is a key proof point that their interconnect technology supports the flexibility and scalability with the lowest power consumption sought by hyperscalers as they optimise their data centres for AI / ML workloads,” said Vladimir Kozlov the founder and CEO of Lightcounting.

 Ranovus will demonstrate its Odin optical interconnect CPO, NPO and 800Gbits per second DR8+ pluggable module portfolio at the Ranovus booth 2019 and the GlobalFoundries booth 5216.  

http://www.ranovus.com

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HighTec wins the race to offer Rust Compiler for Infineon Aurix microcontrollers

Believed to be the first Rust compiler available for the 32bit Aurix multi-core architecture, HighTec EDV-Systeme said it enables the use of the Rust compiler with Aurix TC3x and TC4x microcontrollers. The pairing is designed for the development of safe, secure and smart mobility and industrial applications.

The Rust compiler joins HighTec’s portfolio of LLVM open-source based C/C++ compiler tools. This new offering targets customers in the automotive and industrial sectors which can now take advantage of the security and safety benefits of both the Aurix multi-core architecture and HighTec’s LLVM-based Rust compiler.

Recently, the programming language Rust has seen significant growth in popularity, driven by the increasing need for safe and secure systems, reported HighTec. Its memory management features, such as its ownership model, help prevent the types of vulnerabilities that are often the root cause of system failures and security breaches, said the company. 

Infineon’s Aurix microcontroller family has found applications in smart mobility applications in particular, where stringent safety and security requirements are required. The announcement means the robust safety and security features of the Rust programming language are combined with the ASIL D/SIL 3 certified Aurix TC3x and TC4x microcontrollers.

HighTec is the only compiler provider to be an Infineon Preferred Design House. Its Rust compiler for Aurix TC3x and TC4x leverages the modern open source LLVM technology, with an efficient backend. The compiler is characterised by its rapid build system and advanced code optimisations, which are specifically tailored to the architecture-specific functions of the Aurix microcontrollers. HighTec is able to accelerate the development and certification of safety critical applications across a range of industries, including automotive and industrial automation. 

The original HighTec C/C++ development platform is widely used by automotive manufacturers and Tier One suppliers. By 2024, HighTec plans to offer a safety qualified Aurix Rust compiler.

HighTec’s initial Aurix Rust package includes the Rust compiler tools consisting of  cargo build system, Rust libraries, hardware abstraction, and board support package (BSP) for TC375. There are also integrated examples including the use of C based peripheral drivers and documentation.

The examples have been designed in co-operation with Elexir. For Rust HLL (high level language) debugging, developers can use the Lauterbach Trace32 debugger. 

http://www.hightec-rt.com

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SiT7910 Super-TCXO sets timekeeping benchmark, says SiTime 

Designed for aerospace and defence applications, the latest member of the Endura family by SiTime enables faster GPS signal acquisition and locking. The SiT7910 sets a new performance benchmark for timekeeping components, said the company.

The SiT7910 is part of the SiTime Endura ruggedised family in aerospace and defence devices which use global positioning system (GPS) signals, such as ruggedised handheld radios, ground vehicles and sensors. All can acquire and lock to GPS more quickly and securely with the 25 times higher precision of this Super-TCXO, said SiTime.

 “The GPS signal is ubiquitous and is a crucial part of national security, everyday communications, financial systems, and power grid operations,” said Piyush Sevalia, executive vice president of marketing at SiTime. “However, it is susceptible not just to environmental disruptions but also to jamming and spoofing”. It requires precision timekeeping, which ensures the faster and more secure acquisition of, and locking to GPS signals, even in the harshest of environmental conditions. The SiT7910 Super-TCXO uses SiTime’s MEMS, analogue and systems technologies.

Key features include 32.768kHz frequency and ±0.2 ppm frequency stability over -55 to +105 degrees C with performance up to 25 times better than legacy quartz technology, reported SiTime. The device maintains one second of accuracy for one year, versus legacy quartz devices that can only maintain it for one to 14 days.

The SiT7910 also has 20 ppb per g g-sensitivity for resilience in high-vibration environments. It also has low power consumption, typically 6.0 microA and ±5 ppm frequency ageing over 20 years.

Operating supply voltage is 1.62 to 3.63V.

The Super-TCXO is packaged in a space saving 2.5 x 2.0mm package and is Pb-free, RoHS, and REACH-compliant

The Endura SiT7910 is sampling now. Volume production is expected in Q2, 2023.

SiTime is a precision timing company, with products designed to enable customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. 

http://www.sitime.com

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