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32-bit MCU offers functional safety, cybersecurity and AutoSAR compatibility

Fri, Sep 16, 2022

To support developers’ work to automate and connect end applications, Microchip has introduced the PIC32CM JH microcontroller. The 512kbyte flash, 5.0V, Dual CAN FD device delivers features typically only available on more expensive, higher performance devices, said Microchip.

Automation and connectivity rely on industry standards related to functional safety and cybersecurity protection to ensure products operate safely and securely. To provide manufacturers with an MCU equipped with components that meet ISO 26262 functional safety and ISO/SAE 21434 cybersecurity engineering standards, the PIC32CM JH is the industry’s first MCU-based on the Arm Cortex-M0+ architecture with AutoSAR support, memory built-in self test (MBIST) and secure boot.

The PIC32CM JH is compatible with AutoSAR, an open software architecture, providing suppliers with the ability to change to lower-level hardware while keeping the original application code for ease of migration. AutoSAR-ready is designed to streamline the development process and reduce overall costs. When using AutoSAR, Microchip offers ASIL B microcontroller abstraction layers (MCALs) for functional safety applications, providing the lower-level hardware interface to the MCU.

Automotive industry OEMs require both functional safety and cybersecurity protection for many in-vehicle applications including touch buttons and touch wheels, door controls and console controls, and body applications such as advanced driver assistance systems (ADAS). Pairing the PIC32CM JH with one of Microchip’s Trust Anchor TA100 CryptoAutomotive security ICs, complies to ISO/SAE 21434, the new Cybersecurity standard for automotive. The TA100 employs secure hardware-based cryptographic key storage and cryptographic counter measures to eliminate potential back doors linked to software weaknesses.

Rod Drake vice president of Microchip Technology’s 32-bit MCU business unit, commented: “OEMs and other manufacturers now have the option to use an entry-level Arm Cortex-M0+ based MCU to meet compliance requirements previously only available on higher-end MCUs.”

The secure boot authenticates the code and prevents malicious code from being loaded onto the MCU. Other hardware features on the PIC32CM JH MCU are error correction code (ECC) with fault injection, loopbacks on the communications interfaces, system memory protection unit and MBIST.

MBIST is the industry standard method of testing embedded memories and can quickly test the integrity of the SRAM to ensure it is functioning properly before the code is run to mitigate failures. To support developers with implementation, the PIC32CM JH has a safety manual, failure modes effects and diagnostic analysis (FMEDA) and diagnostic code targeting to ISO 26262 ASIL B.

The PIC32CM JH also includes advanced touch with Driven Shield Plus, for noise and water tolerant operation. This feature is necessary for home appliances, industrial and automotive applications requiring touch operation in harsh environments.

Microchip also provides the PIC32CM JH01 Curiosity Pro development kit (Part number EV81X90A) to support the PIC32CM JH MCU.

The PIC32CM JH MCU and EV81X90A are available now.

http://www.microchip.com

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Image sensor is adaptive for all vehicle occupants

Fri, Sep 09, 2022

In-car safety and comfort in automotives is advanced with the VD/VB1940 DMS (driver monitoring system) sensor, a hybrid sensor for interior monitoring, announced by STMicroelectronics.

Leading automotive markets start to mandate driver monitoring systems (DMS) reported STMicroelectronics. While DMS promises greater road safety by assessing driver alertness, ST said that its next-generation dual image sensor monitors the full vehicle interior, i.e., the driver and all passengers. The sensor enables new applications such as passenger safety-belt checks, vital-sign monitoring, child-left detection, gesture recognition and high-quality video/picture recording.

The image sensor uses ST’s second-generation 3D-stacked back-side illuminated (BSI) wafer technology, which maximises the optical area and on-chip processing in relation to die size. This lets the sensor perform sophisticated algorithms locally for optimal performance in both colour and near-infra-red (NIR) imaging, saving power and relieving demand for an external co-processor.

Algorithms performed on-chip include Bayer conversion and HDR merging for optimal image-quality and frame rate. On-chip Bayerisation processing enables the user to reshuffle the colour pixels of the RGB NIR 4X4 pattern into RGGB format compatible with a range of SoCs. Local processing also handles independent colour and NIR pixel-exposure optimisation for optimum image quality in both modes, as well as smart upscaling to maximise NIR image resolution by capturing extra NIR information from RGB pixels.

The VD/VB1940 sensor combines the sensitivity and high resolution of infra red sensing with high dynamic range (HDR) colour imaging in a single component. It can capture frames alternatively in rolling-shutter and global-shutter modes. With 5.1Mpixels, it captures the high dynamic range (HDR) colour images needed for an occupant monitoring system (OMS) in addition to the high-quality NIR images typically captured by standard DMS sensors. DMS uses NIR imaging to analyse driver head and eye movements in all lighting conditions.

Offered in both bare wafers (VDB1940) and packaged in BGAs (VB1940), samples are available now and mass production is planned to meet model-year 2024 vehicles being designed now.

Qualified to AEC-Q100, the VD/VB1940 is ISO 26262 compliant to facilitate use in functional-safety systems up to ASIL-B.

http://www.st.com

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Andes Technology teams up with Green Hills Software for automotive RISC-V

Wed, Aug 17, 2022

RISC-V CPU IP vendor, Andes Technology, and Green Hills Software will collaborate to develop an integrated, secure hardware-software platform for automotive applications.

Andes Technology’s ASIL-certified AndesCore 25-Series RISC-V processor family will be integrated with Green Hills’ safety-certified µ-velOSity real time operating system (RTOS), the ASIL-certified MULTI development environment with advanced system-level debugging and analysis tools and C/C++ optimising compilers, along with the Green Hills probe for JTAG and trace target connections.

The combined hardware and software platform is designed for SoC companies and end customers to create market-leading 32bit / 64bit RISC-V-based SoCs targeting critical functions requiring ISO 26262 ASIL B to ASIL D. The offering will be used for vehicle electronics requiring compact and cost-sensitive SoCs that are still capable of ASIL certification, confirmed Green Hills Software.

The CPU IP cores are based on AndesStar V5 architecture incorporating RISC-V technology. Its five-stage pipeline is optimised for high operating frequency and high performance, with a small gate count. The 25-Series supports optional single- and double-precision floating point instructions. It also offers branch prediction for efficient branch execution, instruction and data caches, local memories for low-latency accesses, and ECC for L1 memory soft error protection.

Through design guidance and training, Green Hills Software’s services teams help customers achieve their own tailored levels of safety, security, and performance, with the highest developer productivity.
Andes Technology claims to be the first RISC-V processor IP vendor to receive ASIL D process certification for both hardware (ISO 26262-5) and software (ISO 26262-6). The functional safety-enabled Andes Technology and Green Hills Software offering is expected to be available for general licensing by the second half of 2022.

“AndesCore RISC-V processor IP with safety enhancement has already been adopted by several early customers,” said Dr Charlie Su, Andes technology president and CTO. “The . . . partnership with Green Hills Software enables us to further offer comprehensive and robust development support for our customers. We welcome the benefits that Green Hills Software’s mature functional safety solutions bring to the RISC-V community to speed up the adoption of RISC-V safety-related applications,” he added.

Expanding the Green Hills’ portfolio to include the latest advanced safety-certified RISC-V AndesCore IP in a combined hardware-software solution means “SoC providers using the AndesCore 25-Series family can immediately start developing their next generation vehicle ECUs with the highest performing, lowest power offerings, while reducing their customers’ time to market and development costs by offering integrated and optimised production-proven solutions,” said Dan Mender, vice president, business development, Green Hills Software.

http://www.ghs.com

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AMD and ECARX collaborate on immersive cockpit in-vehicle computing

Fri, Aug 05, 2022

AMD and mobility technology company, Ecarx, will work together on an in-vehicle computing platform for electric vehicles (EVs), expected to be in mass production in late 2023. The Ecarx digital cockpit in-vehicle platform will be offered with AMD Ryzen Embedded V2000 processors and AMD Radeon RX 6000 Series GPUs (graphic processor units) and Ecarx hardware and software.

The digital cockpit’s features will include driver information mode, heads-up display, rear seat entertainment, multiple-displays, multi-zone voice recognition, gaming and a 3D user experience.

Ecarx is AMD’s first strategic ecosystem partner in China for the digital cockpit.

“The global automotive industry is transforming towards an intelligent future at an unprecedented pace with demand for computing power and graphics capabilities rapidly increasing,” said Ziyu Shen, chairman and CEO of Ecarx. “With this collaboration, we will further enable OEMs and tier 1 suppliers to enhance their digital cockpit experiences as they seek to create greater consumer value through intelligent connected cars.”

“EV adoption is now a key underlying factor for growth in the automotive semiconductor market and the associated semiconductor demand is forecast to grow at a CAGR [compound annual growth rate] of 31 per cent over 2021 to 2026,” said Asif Anwar, executive director – PBCS and EVS, Strategy Analytics. He believes domain- and zonal-based architecture will drive adoption of the digital cockpit, ADAS (advanced driver assistance systems) and the connected vehicle.

The Ryzen Embedded V2000 Series processors are the second generation designed for automotive in-vehicle infotainment and instrumentation applications. They are also used in industrial edge, thin client and miniPC systems. The processors can power up to four independent displays simultaneously in 4K resolution; it is equipped with up to eight CPU cores and seven GPU compute units. A single AMD Ryzen Embedded V2000 Series processor provides up to two times the multi-threaded performance per Watt, up to 30 per cent better single-thread CPU performance and up to 40 per cent better graphics performance over the previous generation.

AMD Radeon RX 6000 Series GPUs are built upon the AMD RDNA 2 graphics architecture. This is, said AMD, the only graphics architecture that spans from next-generation desktop PCs, laptops and consoles to mobile devices and automotive infotainment systems. It offers up to two time higher performance) and up to 50 per cent more performance per Watt in select titles compared to the previous generation AMD RDNA architecture.

Ecarx’s current core products include infotainment head units (IHU), digital cockpits, vehicle chipsets, a core operating system and integrated software stack. It is also developing a full-stack automotive computing platform.

Its technology has been integrated into more than 3.2 million cars worldwide.

For more than 50 years, AMD has developed computing, graphics and visualisation technologies.

http://www.amd.com

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32-bit MCU offers functional safety, cybersecurity and AutoSAR compatibility

Image sensor is adaptive for all vehicle occupants

Andes Technology teams up with Green Hills Software for automotive RISC-V

AMD and ECARX collaborate on immersive cockpit in-vehicle computing

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