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IP innovates with visually lossless image compression for GPUs

Fri, Nov 02, 2018

Providing a reduction in memory footprint, Imagination Technologies has announced PowerVR PVRIC4 technology which provides cost savings for memory and bandwidth-constrained devices such as DTVs, smartphones and tablets.

The company explains that its new generation of powerful image compression technology will enable SoC to reduce costs without a discernable loss of image quality. PVRIC4 enables random-access visually lossless image compression, ensuring bandwidth and memory footprint savings of at least 50 per cent, confirms Imagination, and enables systems to overcome performance bandwidth constraints.

PVRIC4 is provided as a standalone IP block for SoC manufacturers, already used by partners.

PVRIC4 features a dual-pipeline framebuffer compression engine. A new lossy pipeline, used only if the lossless pipeline does not achieve 50 per cent compression, ensures that even difficult to compress ‘noisy’ images are compressed with the highest fidelity. A decision logic block determines which output should be used to guarantee the compression ratio, and highly tuned algorithms ensure the image quality change is imperceptible. The hybrid solution offers SoC manufacturers high fidelity ensuring bandwidth and frame buffer allocation savings on graphics and video content, says the company, all performed in hardware and achieved without any performance overhead.

PVRIC4’s bandwidth savings translate into better battery life and cost savings for system manufacturers. RAM and bandwidth can be freed for other uses, such as enabling simultaneous fast 5G downloads while the GPU is in use, or a reduction in the number of DRAM devices used in the system.

PVRIC4 will be available as a feature in next-generation PowerVR GPUs and is available for licensing now as a standalone IP block.

Imagination Technologies provides a range of silicon IP (intellectual property) including key processing blocks needed to create the SoCs that power all mobile, consumer and embedded electronics.

Imagination Technologies was acquired in 2017 by Canyon Bridge, a California-headquartered, global private equity investment fund.

http://www.imgtec.com

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NoC IP combines with AI package for neural networking

Thu, Nov 01, 2018

Commercial interconnect IP from Arteris IP, is claimed to accelerate the development of next-generation deep neural network (DNN) and machine learning systems. The FlexNoC version 4 interconnect IP and the companion AI Package. FlexNoC 4 and the AI Package (FlexNoC 4 AI) implement new technologies that ease the development of today’s most complex AI, deep neural network (DNN), and autonomous driving SoCs, explains Arteris.

Arteris IP created the new technologies in FlexNoC 4 AI based on its learning from customers, including Mobileye, which recently licensed Arteris IP FlexNoC and Ncore interconnect IP for its next-generation EyeQ systems.

Using automated topology generation for mesh, ring and torus networks, the FlexNoC 4 AI enables SoC architects to generate AI topologies automatically and also edit generated topologies to optimise each individual network router, if desired.

The FlexNoC 4 AI intelligent multicast optimises the use of on-chip and off-chip bandwidth by broadcasting data as close to network targets as possible. This allows for more efficient updates of DNN weights, image maps and other multicast data.

Another feature, source synchronous communications, helps avoid clock tree synthesis, physical placement, and timing closure problems when spanning long distances on AI chips, which can be larger than 400mm².

The VC-Link virtual channels allow long physical links to be shared in congested areas of the die while maintaining quality of service (QoS).

There is also support for HBM2 and multichannel memory and for up to 2048-bit wide data.

The FlexNoC 4 interconnect IP and the FlexNoC 4 AI Package are available immediately.

Arteris IP provides network in chip (NoC) interconnect IP to accelerate SoC semiconductor assembly for a range of applications from artificial intelligence (AI) to automobiles, mobile phones, IoT, cameras, SSD controllers, and servers. Its customer base include Samsung, Huawei, HiSilicon, Mobileye and Texas Instruments. The IP product line can help customers obtain lower power, higher performance, more efficient design reuse and faster SoC development, to lower development and production costs.

http://www.arteris.com

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Microcontroller secures updates for the connected car

Thu, Nov 01, 2018

Large on-chip memory and support for secure over the air (OTA) updating of electronic control unit (ECU) software lets vehicle manufacturers streamline maintenance using the latest addition, the SPC58NH92x microcontrollers, says STMicroelectronics.

The EVITA (e-safety vehicle intrusion protected applications) -compliant hardware security module keeps connected cars and occupants safe, says STMicro. Being EVITA Full compliant, it implements industry-leading attack prevention, detection, and containment techniques, adds the company.

As critical vehicle powertrain, body, chassis, and infotainment features increasingly become defined by software, securely delivering updates such as fixes and option packs OTA are cost-efficient and convenient. The SPC58 H has been added to the Chorus series of automotive microcontrollers. It has three high-performance processor cores, more than 1.2Mbyte RAM and powerful on-chip peripherals, and can run multiple applications concurrently to allow more flexible and cost-effective vehicle-electronics architectures.

Two independent Ethernet ports provide high-speed connectivity between multiple Chorus chips throughout the vehicle and enable responsive in-vehicle diagnostics, adds STMicro. There are also 16 CAN-FD and 24 LINFlex interfaces, enabling Chorus to act as a gateway for multiple ECUs and support smart gateway functionality via two Ethernet interfaces which are also on-chip.

To protect connected-car functionalities and allow OTA updates to be applied safely, the Chorus chip contains a hardware security module (HSM) which is capable of asymmetric cryptography.

The SPC58NH92x, has 10Mbyte on-chip flash and features a triple-core architecture clocking at 200Mhz equipped with more than 1.2Mbyte RAM, delivering up to 1763 CoreMark containing ST’s Power Architecture z4 core, which gives developers the flexibility to host multiple applications on one microcontroller, or to run multiple tasks concurrently. The device offers also ASIL-D safety capabilities.

The SPC58NH92x’s context-swap mechanism allows current application code to run continuously even while an update is downloaded and made ready to be applied later at a safe time. The older software can be retained, giving the option to roll-back to the previous version in an emergency. Hyperbus and eMMC/SDIO high-speed interfaces to off-chip memory are also integrated, enabling further storage expansion.

Configurable smart low-power modes enable the SPC58 microcontroller to perform critical functions even when in standby.

http://www.st.com

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HiFi DSP boosts audio and neural network processing

Thu, Nov 01, 2018

The first DSP optimised for speech and audio processing, the Tensilica HiFi 5 is the fifth generation HiFi DSP from Cadence. It is the first IP core optimised for high-performance far-field processing and artificial intelligence (AI)-based speech recognition processing, according to Cadence. This version of the HiFi DSP offers two times audio processing and four time neural network (NN) processing improvements compared with the earlier HiFi 4 DSP. The device can be used for voice-controlled user interfaces in digital home assistants and automotive infotainment.

Advanced DSP algorithms are rapidly evolving to eliminate noise and isolate the speakers’ voice for increased understanding, requiring higher processing capabilities and improved energy efficiency. At the same time, NN-based speech recognition algorithms are performing more tasks locally, rather than in the cloud, due to concerns of latency, privacy and network availability.

The DSP includes five very long instruction word (VLIW)-slot architecture capable of issuing two 128-bit loads per cycle. There is also twice the MAC capability of the HiFi 4 DSP for pre- and post-processing, including support for eight 32 x 32-bit or 16 16 x 16-bit MACs per cycle, optional eight single-precision floating-point MACs per cycle, four times MAC capability, compared with the HiFi 4 DSP, for NN processing.

The HiFi NN library offers an optimised set of library functions commonly used in NN processing (especially speech). These library functions can easily be integrated into popular machine learning frameworks.

The DSP also has software compatibility with the complete HiFi product line totalling over 300 HiFi-optimised audio and voice codecs and audio enhancement software packages.

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https://www.cadence.com

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IP innovates with visually lossless image compression for GPUs

NoC IP combines with AI package for neural networking

Microcontroller secures updates for the connected car

HiFi DSP boosts audio and neural network processing

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