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Aetina showcases transportation options at Computex 2019

Mon, May 20, 2019

Smart transportation and smart logistics of artificial intelligence (AI) with vehicle cameras will be on display at Computex 2019 at the Aetina stand (H 1-K0806) in Taipei (28 May to 1 June).

The company has identified intelligent transportation and logistics will be the main drivers of smart cities and e-commerce.

The edge AI computing company has worked with a third-party partner to embed AI for road and transit products.

For transportation, Aetina bases its edge computing on the Jetson for data processing when it is used to infer road situations, such as to calculate traffic flow, vehicle recognition, and traffic law enforcement. As well as immediately addressing an urban area’s traffic issues and adjusting conditions for short term gain, this can also help the transportation scheme in the city over a longer period of time and in the planning of future schemes.

In logistics, whether robotics in a warehouse, tracking or monitoring systems, AI can improve edge computing, says Aetina. Aetina has collaborated with ecosystem partners to deliver a 10 meter length of FPD link cameras and internet of vehicles (IoV) hardware, for AI logistics.

According to Aetina’s general manager, Joe Lo, “Everything will not only get onto the internet but will also have the ability to infer, to create more possibilities for a city”.

Aetina was founded in Taiwan in 2012. It is a provider of high-performance general purpose graphics processing units (GPGPUs) and Jetson edge AI computing products for embedded applications.

Aetina focuses on the industrial market, providing industrial grade components and is also an integrator of artificial intelligent IoT, offering a smart, innovative, and reliable solutions of GPUs.

http://www.aetina.com

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Lens array for optical transceivers include mirror

Fri, May 17, 2019

Optical networks for data centres can maximise density in optical transceivers using the FLHL2 series lens array with mirror from Alps Alpine.

IoT technology and artificial intelligence (AI) has increase IP traffic globally. This is expected to be increased further by the introduction of 5G mobile and wireless networks. As a result, optical transceivers used in facilities like data centres will need to be much faster and have higher density, demanding even greater size reductions and high-density mounting of components.

The FLH2 series was developed by Alps Alpine in responses to these trends. The lens array has a 0.75mm lens pitch and integrates condenser lens and mirror components of an optical transceiver receiver. The array measures just 1.3 x 1.3 x 3.5mm. Now, instead of have to position the lenses and mirror separately to convey light to the photodiode, this integrated lens reduces the number of parts and shortens the optical distance to contributing to downsizing the optical transceivers. Having fewer components also reduces the work required for transceiver assembly, leading to lower costs, adds Alps Alpine.

The lead-free glass used is (RoHS-compliant).

Mass production will begin in August this year and Alps Alpine has also announced that it will develop lens arrays with 0.5mm and 0.25mm lens pitches in anticipation of future market requirements for downsizing and multi-channel transceivers as IoT spreads and 5G services are introduced.

Alps Alpine developed one of the world’s smallest glass lenses for submarine cables in 2000.

Alps Alpine was formed on January 1, 2019, when Alps Electric and Alpine Electronics integrated. The company has over 42,000 employees.

Alps Alpine has expertise in core devices, system design and software development and serves the automotive, mobile devices and consumer electronics markets, as well as new sectors such as energy, healthcare and industry.

http://www.alpsalpine.com

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RX72T motor control MCUs serve industrial robots

Fri, May 17, 2019

32-bit motor control microcontrollers (MCUs) from Renesas Electronics have dedicated hardware accelerator IP to perform the complex, high-speed computations required for motor control in robots and other industrial equipment.

The RX72T series achieves an 1160 CoreMark score as measured by EEMBC benchmarks, claimed to be the highest level for a 5.0V MCU operating at 200MHz.

The RX72T extends the migration path across the RX family for low-cost designs in compact industrial robots, explains Renesas.

Typical applications are servo systems. The rising demand for compact industrial robots is a target application, where high-precision control of the position, direction, speed, and torque of the motor is required to implement complex motions.

The RX72T MCUs include dedicated accelerator hardware that enables the high-speed position control and speed control calculations required for implementing servo motor control in compact industrial robots. The current control loop calculation can be performed in less than 1.5 micro seconds. This presents a choice for users to independently develop servo systems where previously they only had the option of purchasing existing servo systems.

Implementing calculations in software can require excessive computing time. However, completely hardware-based calculations can adversely affect the flexibility to implement user control operations. The RX72T MCUs, Renesas implement only the single-precision floating point trigonometric function (sin, cos, arctan, hypot) and a register bank saves the function in hardware as dedicated IP. This retains flexibility while increasing the calculation speed, says Renesas. The save function increases the speed and precision of interrupt handling, improving the device computation performance, Renesas adds. The MCUs also include 200 MHz PWM inverter control timers with up to four channels of three-phase control, two channels of five-phase control or 10 channels of single-phase control.

Pairing Renesas’ Failure Detection e-AI Solutions for motors with the RX72T MCUs can improve productivity, says Renesas. Characteristic data (current and speed values) that indicate the motor state can be used directly to implement motor control and e-AI-based failure detection with a single MCU. The MCUs also feature hardware-based system failsafe functions and a hardware cryptography module that can be used to encrypt/decrypt communications data.

Renesas also provides the Renesas Motor Workbench 2.0 for real-time debugging and an RX72T CPU card that supports the 24 V motor control evaluation kit.

The MCUs will be available in mass production quantities beginning in Q4 2019.

https://www.renesas.com

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eSilicon announces production of FinFET ASIC for 5G infrastructure

Wed, May 15, 2019

A large 2.5D FinFET ASIC targeting the 5G infrastructure market is entering final product qualification, announces eSilicon. The company has collaborated with the ASE Group for packaging, Rambus for the high-performance SerDes, Samsung for the 14nm FinFET ASIC fabrication and HBM memory stacks and UMC for the silicon interposer.

The design, which is over 600mm2, contains multiple HBM2 memory stacks on a silicon interposer, employs over 100 lanes of SerDes and contains over 800Mbit of embedded SRAM.

“Designs of this size require specialised analysis and materials, so collaboration between ecosystem players has become more crucial than ever,” said Calvin Cheung, vice president of engineering at ASE Group.

“Rambus’ high performance and flexible SerDes technology, with a large number of SerDes lanes running at various speeds, is a key enabler for this complex ASIC,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are excited to collaborate with our ecosystem partners on the strategic elements to drive the next-generation 5G network growth.”

“This is one of the largest dies we have produced in this 14nm node,” said Hong Hao, senior vice president of Foundry Marketing at Samsung Semiconductor.

Pablo Temprano, Samsung Semiconductor’s vice president of memory marketing added: “The 5G market will mark a new era of technological efficiency for which this 2.5D FinFET ASIC is set to help lead the way.”

“Many 5G designs will require 2.5D technology with a silicon interposer,” said Walter Ng, vice president of sales at UMC. “UMC’s technology provides a critical enabler for these designs.”

Ajay Lalwani, vice president of global manufacturing operations at eSilicon, explained: “Getting this design into production was a real team effort between eSilicon and our ecosystem partners. This teamwork, and the resultant success of this complex part in the end system is the new definition of ASIC success.”

eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Its ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimised 16, 14 or 7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialised memory compilers and I/O libraries. eSilicon’s neuASIC platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets.

http://www.esilicon.com

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Aetina showcases transportation options at Computex 2019

Lens array for optical transceivers include mirror

RX72T motor control MCUs serve industrial robots

eSilicon announces production of FinFET ASIC for 5G infrastructure

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