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Believed to be the first automotive-qualified single-chip GNSS (Global Navigation Satellite System) receiver to integrate triple-band positioning measurement engine, the STA8135GA has been developed by STMicroelectronics. It has a performance comparable to the highest-accuracy surveying / mapping instruments, says the company and delivers high-quality position data for advanced driving systems.

The IC is the latest member of the company’s Teseo V family. In addition to the integrated triple-band positioning measurement engine on-chip, it also has standard multi-band position-velocity-time (PVT) and dead-reckoning.

Triple band has historically been used in professional applications such as surveying, mapping, and precision agriculture that demand millimeter accuracy with minimal reliance on correction data. Until now, this was only available in chipsets or modules, which are typically larger and more expensive than this single-chip device, says ST. The triple-band enables the receiver to efficiently acquire and track the largest number of satellites in multiple constellations simultaneously for performance in difficult conditions such as in urban canyons and under tree cover.

The STA8135GA also integrates separate low-dropout (LDO) voltage regulators on-chip to supply the IC’s analogue circuitry, digital core, and I/O transceivers which simplifies the external power supply. The receiver can track satellites in GPS, Glonass, BeiDou, Galileo, QZSS, and NAVIC / IRNSS constellations.

The STA8135GA helps driver-assistance systems to make decisions using the multi-constellation receiver to deliver raw information for the host system to run any precise-positioning algorithm, such as PPP / RTK (precise point positioning / real-time kinematic). The STA8135GA also enhances the performance of in-dash navigation systems, telematics equipment, smart antennas, and V2X communication systems, as well as marine navigation systems, drones, and other vehicles.

According to Luca Celant, general manager, ADAS, ASIC and Audio Division, Automotive and Discrete Group, STMicroelectronics: “The high precision and single-chip integration . . . . enables the creation of reliable and affordable navigation systems that enable vehicles to be safer and more context aware”. The in-house design resources and processes for high-yield manufacturing are credited with making this industry-first possible, he added.

The STA8135GA is housed in a 7.0 x 11 x 1.2mm QFN package. Samples are available now and full qualification AEC-Q100 and start of production is scheduled for Q1 2022.

http://www.st.com

Purpose-built for high performance computing (HPC) and big data workloads, the Aleveo U55C was unveiled by Xilinx at SC21. 

The data centre accelerator card was launched alongside a new standards-based, API-driven clustering for deploying FPGAs at massive scale. 

The Alveo U55C accelerator is the company’s most powerful Alveo accelerator card to date and offers the highest compute density and HBM capacity in the Alveo accelerator portfolio. Used with Xilinx RoCE v2-based clustering, customers with large-scale compute workloads can now implement powerful FPGA-based HPC clustering using an existing data centre infrastructure and network, says Xilinx. 

“Scaling out Alveo compute capabilities to target HPC workloads is now easier, more efficient and more powerful than ever,” said Salil Raje, executive vice president and general manager, Data Center Group at Xilinx. “Architecturally, FPGA-based accelerators like Alveo cards provide the highest performance at the lowest cost for many compute-intensive workloads. By introducing a standards-based methodology that enables the creation of Alveo HPC clusters using a customer’s existing infrastructure and network, we’re delivering those key advantages at massive scale to any data centre,” he said.  

The Alveo U55C card delivers more parallelism of data pipelines, superior memory management, optimised data movement throughout the pipeline, and the highest performance-per-watt in the Alveo portfolio. 

The single-slot full height, half length (FHHL) form factor card has a low 150W (max) power. It doubles the HBM2 to 16Gbyte compared to its predecessor, the dual-slot Alveo U280 card. The U55C therefore provides more compute in a smaller form factor to create dense Alveo accelerator-based clusters. Target applications are high-density streaming data, high I/O math and big compute tasks like big data analytics and AI applications.

Leveraging RoCE v2 and data centre bridging, coupled with 200Gbits per second bandwidth, the API-driven clustering enables an Alveo network that competes with InfiniBand networks in performance and latency, with no vendor lock-in, says Xilinx. MPI integration allows for HPC developers to scale out Alveo data pipelining from the Vitis unified software platform. Using existing open standards and frameworks, it is now possible to scale out across hundreds of Alveo cards regardless of the server platforms and network infrastructure and with shared workloads and memory, Xilinx advises.

Software developers and data scientists can unlock the benefits of Alveo and adaptive computing through high-level programmability of both the application and cluster using the Vitis platform​. Vitis supports AI frameworks, like Pytorch and Tensorflow as well as high-level programming languages like C, C++ and Python, allowing developers to build domain solutions using specific APIs and libraries. Alternatively Xilinx software development kits can be used to accelerate targeted HPC workloads within an existing data centre. 

The Alveo U55C card is currently available via the company’s website and through authorised distributors. It is also available for evaluation via public cloud-based FPGA-as-a-service providers, as well as select co-location data centres for private previews. Clustering is available now for private previews, with general availability expected in Q2 2022. 

http://www.xilinx.com