SoC uses computing-in-memory for speech processing at the edge

Computing-in-memory technology is poised to eliminate the massive data communications bottlenecks associated with AI speech processing at the network’s edge, said Witinmen. The company has worked with Microchip Technology’s subsidiary Silicon Storage Technology (SST) to develop an embedded memory that simultaneously performs neural network computation and stores weights. Microchip Technology announced that its SuperFlash memBrain neuromorphic memory has been combined with the Witinmem neural processing SoC. The SoC is claimed to be the first in volume production that enables sub-mA systems to reduce speech noise and recognise hundreds of command words, in real time and immediately after power-up.

Microchip has worked with Witinmem to incorporate Microchip’s memBrain analogue in-memory computing, based on SuperFlash technology, into Witinmem’s low-power SoC. The SoC features computing-in-memory technology for neural networks processing including speech recognition, voice-print recognition, deep speech noise reduction, scene detection, and health status monitoring. Witinmem is working with multiple customers to bring products to market during 2022 based on this SoC.

“Witinmem is breaking new ground with Microchip’s memBrain solution for addressing the compute-intensive requirements of real time AI speech at the network edge based on advanced neural network models,” said Shaodi Wang, CEO of Witinmem. “We were the first to develop a computing-in-memory chip for audio in 2019, and now we have achieved another milestone with volume production of this technology in our ultra-low-power neural processing SoC that streamlines and improves speech processing performance in intelligent voice and health products.”

Microchip’s memBrain neuromorphic memory is optimised to perform vector matrix multiplication (VMM) for neural networks. It enables processors used in battery-powered and deeply-embedded edge devices to deliver the highest possible AI inference performance per Watt. This is accomplished by both storing the neural model weights as values in the memory array and using the memory array as the neural compute element. The result is 10 to 20 times lower power consumption than alternative approaches, claims Microchip, and a lower overall processor bill of materials (BoM) costs because external DRAM and NOR are not required. 

Permanently storing neural models inside the memBrain’s processing element also supports instant-on functionality for real time neural network processing. Witinmem has leveraged SuperFlash technology’s floating gate cells’ non-volatility to power down its computing-in-memory macros during the idle state to further reduce leakage power in demanding IoT use cases.

http://www.sst.com

http://www.microchip.com

http://www.witintech.com

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Open ZR+ QSFP-DD transceivers enhance data centre performance

Small form factor pluggable modules from NeoPhotonic use the Marvell Deneb Coherent DSP (CDSP) to incorporate industry standard open forward error correction (OFEC). The Open ZR+ QSFP-DD transceivers are designed for hyperscale data centre and telecomms networks in metro-regional applications.

They are based on NeoPhotonics’ 400ZR design, optical components and low noise tunable lasers. The company is a contributor to the Open ZR+ Multi-Source Agreement (MSA), which defines interoperability specifications for OpenZR+.

By using OFEC, the rOSNR capability of NeoPhotonics transceivers is improved beyond traditional 400ZR CFEC, allowing for multiple span coverage in amplified networks.  This may be applied to metro and IP-over-DWDM networks with extended-reach scenarios, with data rate coverage from 100 to 400Gbits per second.

There are a number of applications where the fibre reach may not exceed the OIF ZR specifications, explained NeoPhotonics, but because of older fibre, patch panels and other impairments, the link loss and impairment budgets could exceed that of a standard 400ZR link.

The OpenZR+ module can be used for 400G upgrades.  

“NeoPhotonics has developed an OpenZR+ solution to take advantage of the benefits of IP-over-DWDM and because many customers are interested in utilising small form factor coherent modules deeper into their networks,” said Tim Jenks, chairman and CEO of NeoPhotonics.  “Our Open ZR+ QSFP-DD transceivers combine an extended network reach and interoperable OFEC with our proven optical component and transceiver designs to address these needs.

“The ability to transmit 400Gbits per second over distances as long as 800km and more in a cost-effective manner is a real game changer,” concluded Mr. Jenks.

NeoPhotonics develops and manufactures lasers and optoelectronic devices that transmit, receive and switch high-speed digital optical signals for cloud and hyper-scale data centre internet content provider and telecomms networks. The company’s products enable cost-effective, high-speed over distance data transmission and efficient allocation of bandwidth in optical networks.  

NeoPhotonics maintains headquarters in San Jose, California, USA and ISO 9001:2015 -certified engineering and manufacturing facilities in Silicon Valley (USA), Japan and China.  

http://www.neophotonics.com

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NXP integrates AES with EAL3+ for secure contactless MiFare

Claimed to be the most secure member of the MiFare Ultralight family, NXP Semiconductors has integrated Advanced Encryption Standard (AES) with Common Criteria EAL3+ security certification to enhance privacy and security in limited-use contactless tickets, RFID basic guest cards and other limited-use contactless applications.

MiFare Ultralight AES is for limited-use contactless tickets and cards, such as RFID basic guest cards, event tickets, access passes, loyalty cards or transit tickets. IT uses cryptography with sufficient key length recommended by the National Institute of Standards and Technology for secure authentication and protected data access and there is the option to limit negative authentication attempts. 

The ICs offer protected data access based on AES authentication with 128-bit key length and optional Command Counter to limit negative authentication attempts. They also have a configurable secure messaging communication mode with CMAC for integrity protection and a 7-byte UID with optional Random ID support for enhanced privacy. An ECC-based originality signature allows product validation based on public key (pre-programmed). The ICs include a 144-byte EEPROM and are ISO / IEC 14443 A -2 / -3 compliant.

The secure implementation is suitable for guest protection and secure room access or as a secure transport ticket in smart cities.  

Andre Perchthaler, segment manager, MiFare Smart Cities, at NXP, said: “By taking advantage of a single, standard-based encryption method, such as AES, service providers have the benefit of greater fraud prevention, while also being able to streamline integration and key management. With MiFare Ultralight AES, the full MiFare product portfolio now serves AES authentication from single-use up through multi-applications, simplifying access infrastructure, and reducing complexity and maintenance costs.”  

NXP Semiconductors claims to be the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial and IoT, mobile, and communication infrastructure markets. 

http://www.nxp.com

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Stella E MCUs power software-defined EVs

Automotive microcontrollers (MCUs) optimised for electric vehicles (EVs) and centralised (domain and zonal) electronic architectures have been released by STMicroelectronics. According to ST, they enable EVs to become more affordable, drive further and charge faster.

In current EVs, high-efficiency silicon carbide (SiC) -based power modules enable the greatest driving range and faster charging. Until now, they have required dedicated high-speed signal processors to control the advanced SiC power semiconductors. The Stellar E MCUs launched by ST are designed for the next generation of software-defined EVs, integrate high-speed control-loop processing on-chip. A single MCU can control the entire module, says ST, simplifying module design, saving costs and easing compliance with automotive safety and security standards.

The MCUs extend ST’s Arm-based Stellar family. They are a centralised domain and zone controller which simplify automotive electrical architectures for increased power, flexibility and safety, explained ST. 

The MCU family includes the Stellar P series for integration and vehicle control and the Stellar G series for body applications. The Stellar family architecture integrates multiple Arm Cortex cores that deliver high performance with the opportunity for lock-step redundancy and support real-time hardware virtualisation. All Stellar devices are designed for software upgradeability through secure over-the-air (OTA) updates.

The first product in the Stellar E series, the Stellar SR5E1 is optimised for EV on-board chargers (OBC) and general DC/DC converters, is now sampling to lead customers. Full production will begin in 2023. 

The Stellar E (Stellar Electrification MCUs) series are automotive-qualified MCUs that perform the high speed, control loop processing alongside general control in the same chip. 

The MCUs can control multiple power converters, leveraging features including a high speed ADC, a pulse-width modulation (PWM) controller and fast-acting protection circuitry.

The Stellar E series supports the leading automotive standards for functional safety (ISO 26262 ASIL-D), security (HSM -), and industry standard software interoperability (via Autosar 4.3.x), as well as secure OTA update. The Stellar family is supported with an extensive software-development toolchain with a common ecosystem for control and actuation.

http://www.st.com

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