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Cadence has finetuned its RTL-to-GDS digital flow and delivered corresponding 3nm and 5nm rapid adoption kits (RAKs) for Arm Cortex-X4, Cortex-A720 and Cortex-A520 CPUs and Immortalis-G720, Mali-G720 and Mali-G620 GPUs.

This part of Cadence Design Systems’ expanding collaboration with Arm to advance mobile device silicon, providing customers with a faster path to tapeout through the use of Cadence digital and verification tools and the new Arm Total Compute Solutions 2023 (TCS23) for the cores and GPUs.

Cadence delivered comprehensive RTL-to-GDS digital flow RAKs for 3nm and 5nm nodes to help customers achieve power and performance goals using the new Arm TCS23. The Cadence tools optimised for the new Arm TCS23 include the Cadence Cerebrus Intelligent Chip Explorer, Genus Synthesis, Modus DFT software, Innovus implementation system, Quantus extraction, Tempus timing signoff and ECO Option, Voltus IC Power Integrity, conformal equivalence checking and conformal low power. Cadence Cerebrus provided Arm with AI-driven design optimisation capabilities that resulted in 50 per cent better timing, a 10 per cent reduction in cell area and 27 per cent improved leakage power on the Cortex-X4 CPU, empowering Arm to achieve power, performance and area (PPA) targets faster, reported Cadence.

The digital RAKs provide Arm TCS23 users with benefits, for example the AI-driven Cadence Cerebrus automates and scales digital chip design, providing customers with improved productivity versus a manual, iterative approach. Cadence iSpatial technology provides an integrated implementation flow, offering improved predictability and PPA, leading to faster design closure. The RAKs also incorporate a smart hierarchy flow that enables accelerated turnaround times on large, high-performance CPUs. The Tempus ECO Option, which provides path-based analysis, is integrated into the flow for signoff-accurate, final design closure. Finally, the RAKs use the GigaOpt activity-aware power optimisation engine, incorporated with the Innovus implementation system and the Genus Synthesis to dramatically reduce dynamic power consumption.

Arm used the Cadence verification flow to validate the Cortex-X4, Cortex-A720 and Cortex-A520 CPU-based and Immortalis-G720, Mali-G720 and Mali-G620 GPU-based mobile reference platforms. The Cadence verification flow supports Arm TCS23 and includes the Cadence Xcelium logic simulation platform, Palladium Z1 and Z2 Enterprise emulation platforms, Helium Virtual and Hybrid Studio, JasperÒ formal verification platform and Verisium Manager planning and coverage closure tools.

The Cadence verification flow lets Arm TCS23 users improve overall verification throughput and leverage advanced software debug capabilities. Cadence also validated that Cadence Perspec system verifier, VIP and System VIP tools all support TCS23-based designs to enable customers to accelerate time to market when assembling TCS23-based SoCs. The virtual and hybrid platform reference designs include the Arm Fast Models to enable early software development and verification through the Cadence Helium Studio as well as the Cadence Palladium and Protium platforms, also known as the dynamic duo.

The Cadence digital and verification flows support the Cadence Intelligent System Design strategy, which enables customers to achieve SoC design excellence. 

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