HBT power amplifiers deliver 0.5W of linear output power for 5G without DPD

The GRF55xx series of InGaP HBT power amplifiers from Guerrilla RF are the first of a new class of 0.5W linear power amplifiers which target all primary cellular bands spanning 615 to 4200MHz. Guerrilla RF also offers GRF56xx variants which double the series’ output power capabilities.

The linear power amplifiers are intended for 5G wireless infrastructure applications that require exceptional native linearity over temperature extremes of -40 to +85 degrees C. Each can deliver up to 26dBm of output power with better than -45dBc of ACLR performance and EVM (error vector magnitude) levels less than 1.2 per cent, without the aid of supplemental linearisation schemes such as digital pre-distortion (DPD).

The ability to beat the -45dBc ACLR (adjacent channel leakage ratio) performance metric without DPD is critical for size, cost and power-sensitive cellular applications, for example in home and commercial repeaters / boosters, femtocells, picocells and cable loss compensators found in automobiles, explained Guerrilla RF.

The first devices to be formally released are the GRF5607 and GRF5608. The span frequency ranges of 703 to 748MHz and 746 to 830MHz, respectively. They are tuned to operate within the n12, n14, n18, n20 and n28 5G new radio (NR) bands.

The ability to beat the -45dBc ACLR performance metric without DPD is critical for cellular applications like home and commercial repeaters/boosters, femtocells, and picocells, as well as cable loss compensators which are used in conjunction with automotive ‘shark fin’ antennas. In each of these use cases, the sensitivity to cost, power and size constraints prohibits the use of elaborate linearization techniques like DPD. Instead, designers must rely on the power amplifier’s native linearity to meet the stringent emissions mask requirements imposed by the latest 5G standards.

“By essentially doubling the output power, GRF is enabling customers to increase the range of their systems by up to 40 per cent,” said Jim Ahne, Guerrilla RF’s vice president of Automotive and 5G products. “Given that these new devices are pin-pin compatible with the previously released GRF55xx series, customers now have an easy path to upgrading the range capabilities of their existing repeater/booster and compensator platforms,” he added.

The GRF5607 and GRF5608 are supplied in pin-compatible 3.0 x 3.0mm, 16-pin QFN packages.

Samples and evaluation boards are available now for both the GRF5607 and GRF5608. 

https://www.guerrilla-rf.com 

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AMD uses Zen 4c core architecture for EPYC 97X4 data centre CPUs

Two workload optimised processors are based on AMD’s new Zen 4c core architecture. The AMD EPYC 97X4 cloud native-optimized data centre CPUs extend the EPYC 9004 series of processors to deliver the thread density and scale needed for leadership cloud native computing. 

The company has also announced the 4th Gen AMD EPYC processors with AMD 3D V-Cache technology, which are suitable for the most demanding technical computing workloads, said AMD. “Forrest Norrod, executive vice president and general manager, Data Center Solutions business group, AMD, commented: “We closely align our product roadmap to our customers’ unique environments and each offering in the 4th Gen AMD EPYC family of processors is tailored to deliver compelling and leadership performance in general purpose, cloud native or technical computing workloads.” 

The AMD EPYC 97X4 processors, with up to 128 cores, deliver up to 3.7 times throughput performance for key cloud native workloads compared to Ampere . The 4th Gen AMD EPYC processors provide customers up to 2.7 times better energy efficiency and support up to three times more containers per server to drive cloud native applications at the greatest scale. 

At the Data Center and AI Technology Premiere, Meta confirmed that these processors are well suited for mainstay applications such as Instagram and WhatsApp, with “impressive performance gains” compared to 3rd Gen AMD EPYC across various workloads, while offering substantial TCO improvements. 

Technical computing enables faster design iterations and more robust simulations to help businesses design new and compelling products. The 4th Gen AMD EPYC processors with AMD 3D V-Cache technology extend the AMD EPYC 9004 series of processors to deliver the world’s best x86 CPU for technical computing workloads such as computational fluid dynamics (CFD), finite element analysis (FEA), electronic design automation (EDA) and structural analysis. 

Optimised for the most demanding HPC applications, the processors deliver performance gains of up to five times when compared to the previous generation HBv3 and scale to hundreds of thousands of CPU cores.

The 4th Gen AMD EPYC processors are available today and are feature and socket compatible with existing AMD EPYC 9004 series CPU-based systems, for a seamless upgrade path. 

http://www.amd.com

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Riviera-PRO supports system simulation of AMD Versal ACAP designs

Simulation and verification specialist, Aldec has announced that its latest release of Riviera-PRO supports system simulation of Versal Adaptive Compute Acceleration Platform (ACAP) designs.

Versal ACAP, developed by Xilinx/AMD, is an adaptable platform comprising an AI engine, processing system, programmable logic, network on chip (NoC) and hardened domain-specific IPs such as PCIe Gen5 with DMA and CCIX, HBM, 600G Interlaken and 600G Ethernet. It enables heterogeneous computing of complex algorithms and accelerates workloads, such as AI embedded computing and high-performance computing.

Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis hardware emulation flow for testing the interactions between AI engine, the processing system and the programmable logic. The entire hardware emulation setup and system integration is done within the Vitis environment. Vitis runs the AI engineE simulator for the graph application, the Riviera-PRO simulator for the programmable logic kernels, and QEMU (open-source system emulator) for the processing system host application. SystemC models are also available for the AI engine and NoC, and they can also be simulated in Riviera-PRO.

System simulation is critical for any Versal ACAP design because of its complex adaptable architecture and high logic density. The full system design can be tested with full debug visibility much earlier in the project cycle without any physical hardware, explained Aldec. This makes it easier to run more test scenarios, test corner cases, and debug complex problems.

Riviera-PRO also has a mixed-HDL simulation engine, advanced debugging environment using waveform viewer, advanced dataflow, RTL hierarchy, objects viewer, and verification coverage features such as code coverage and functional coverage. There is also comprehensive support for SystemVerilog and UVM for users who need to develop reusable and complex testbench environments.

“The Versal ACAP architecture is revolutionary in the FPGA domain, and a game-changer for heterogeneous computing”, said Louie De Luna, Aldec’s director of marketing. “With Versal, users can customise their own domain-specific architectures for optimised computations of their specific workloads. We are now stepping into the computing era where the differentiation is done in hardware instead of software.”

System simulation can be used to perform algorithmic validation, verify architectural extrapolation, connected hardware platforms and application software.

There are Versal ACAP tutorial designs and steps on how to use Riviera-PRO as the RTL simulator for the Vitis hardware emulation flow on Aldec’s Github.

Riviera-PRO 2023.04 is now available for download and evaluation.

http://www.aldec.com

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Achronix announces FPGA IP blocks with 400 GbE connectivity

FPGA and embedded FPGA (eFPGA) IP provider, Achronix has announced that its suite of flexible FPGA IP blocks, the Achronix Network Infrastructure Code (ANIC) includes 400 Gigabit Ethernet (GbE) connectivity. ANIC IP blocks are optimised to accelerate high performance networking pipelines for Speedster 7t FPGAs and the VectorPath accelerator card.

As the demand for high speed data processing continues to grow exponentially, said Achronix, it has developed its IP to address the evolving needs of the networking industry. Integrating 400 GbE and PCIe Gen 5.0, Achronix empowers data centre operators, cloud service providers and telecommunications companies to create SmartNIC solutions which are scalable and flexible.

With 400 GbE support, the ANIC IP enables fast data transfer rates, allowing organisations to process massive amounts of data in real time. This accelerated network throughput maximises application performance and significantly reduces latency, said the company.

ANIC’s modular architecture enables customers to select SmartNIC components necessary for an application. Each optimised IP block is pre-verified with closed timing to speed design. Coupled with partial reconfiguration (the ability to dynamically change the functionality of a block within the IP design), solutions can be seamlessly modified in the field.

Customers can deploy custom IP functions, such as key value stores, intrusion prevention, de-duplication and other network applications, to provide highly parallelised, value added network solutions at 400 GbE network speeds.

Steve Mensor, vice president of marketing for Achronix Semiconductor described the introduction of 400 GbE as a breakthrough which will allow customers to unlock new levels of performance and address the ever-growing demands of modern data centres and communication networks.

ANIC modular IP runs on Speedster7t AC7t1500 FPGAs and VectorPath S7t-VG6 accelerator cards offering what is claimed to be the industry’s highest performance for networking and compute acceleration applications. The Speedster7t architecture includes a 2D network on chip (2D NoC) that provides 20 Tbits per second of total bandwidth. The 2D NoC offers high speed connectivity between the FPGA fabric and the high speed interfaces including 400 GbE, PCIe Gen 5.0, GDDR6, and DDR4/5. Additionally, Speedster7t FPGAs have machine learning processors (MLPs) distributed across the FPGA fabric. Each MLP is a highly configurable, compute-intensive block, with up to 32 multipliers that support integer formats from four to 32 bits and various floating-point modes including direct support for TensorFlow’s bfloat16 format and block floating-point (BFP) format.

Achronix Semiconductor is a fabless semiconductor company based in Santa Clara, California, USA, offering FPGA-based data acceleration solutions, designed to address high- performance, compute-intensive and real time processing applications. Achronix claims to be the only supplier to have both high-performance, high-density standalone FPGAs and licensed eFPGA IP solutions.

Its portfolio includes Speedster 7t FPGA and Speedcore eFPGA IP as well as  ready-to-use VectorPath accelerator cards targeting AI, machine learning, networking and data centre applications. All Achronix products are fully supported by the Achronix tool suite which enables customers to quickly develop their own custom applications.

Achronix has sales and design teams across the US, Europe and Asia. 

http://www.achronix.com

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