Achronix introduces Speedcore custom blocks to accelerate AI/machine learning
Custom blocks dramatically increase Speedcore eFPGA performance, claims Achronix. The company has introduced Speedcore custom blocks for its eFPGA IP.
Achronix Speedcore eFPGAs accelerate data-intensive artificial intelligence (AI) / machine learning, 5G wireless, advanced driving assistance systems (ADAS), data centre and networking applications. The custom blocks are claimed to improve performance, power, and area and enable functionality that has never before been possible in standalone FPGAs. The Speedcore custom blocks allows customers to gain ASIC efficiency while retaining FPGA flexibility, maintains Achronix for an efficient implementation that minimises power and area while maximising data throughput.
Traditional CPU-based architectures are not scaling to meet the exponential growth in compute demand that is required by the new wave of intelligent data-intensive applications, says Achronix. This is driving the need for new, heterogeneous compute architectures with programmable hardware accelerators. Speedcore eFPGAs deliver the highest-performance and lowest-cost hardware acceleration, claims Achronix. Using Speedcore custom blocks, functions that traditionally ran slowly and consumed significant resources in standalone FPGA fabrics are optimised for performance and minimal die area.
For example, the area of a CNN-based YOLO object recognition algorithm was reduced by over 40 per cent by optimising the DSP and memory blocks for matrix multiplication. In another example, large string search functions that require parallel comparator arrays resulted in area reduction of over 90 per cent when implemented in Speedcore custom blocks. In another example, quoted by Achronix, barrel shifters and bit manipulation structures can be fully implemented in Speedcore custom blocks allowing larger, sophisticated applications in the same area and increasing achievable frequency. In yet another example, the core functionality of a 400Gbit per second packet processing data-path running at 800MHz is implemented in Speedcore custom blocks with the programmable logic managing the analysis and control functionality. Achronix believes that today’s standalone FPGAs cannot support this high throughput for packet processing applications.
Speedcore custom blocks are defined by Achronix with its customers, through a detailed architecture analysis of acceleration workloads. Repeated functions that are performance and/or area bottlenecks are evaluated as candidates to be hardened into Speedcore custom blocks. A new release of ACE design tools that includes the new Speedcore eFPGA with custom blocks is provided to customers for benchmarking and evaluation. If required, the process is iterated to create the optimal solution for the customer’s system.
Achronix ACE design tools support Speedcore custom blocks from design capture to bitstream generation and system debug in the same way as memories and DSP blocks. Achronix creates a graphical user interface for each Speedcore custom block that manages all configuration rules. ACE contains full timing details for all configurations of the Speedcore custom blocks, which allows ACE to complete timing-based place-and-route for designs. Customers can use the powerful Floorplanner tool for design optimisation, and to make regional or site assignments for all block instances. ACE also includes a critical path analysis tool that allows customers to analyse timing. Customers can also use ACE’s powerful SnapShot embedded logic analyser to create complex triggers and show run-time signals within Speedcore.
Speedcore is embedded FPGA (eFPGA) IP that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet individual requirements. Speedcore look-up-tables (LUTs), RAM blocks, DSP64 blocks and custom blocks can be assembled in flexible columns to create the optimal programmable function for any given application.
(Picture: TSMC Fab)
