Ethernet 800G Verification IP meets networking demands

Meeting the increases in bandwidth for video-on-demand, social networking and cloud services, Synopsys has introduced the Native System Verilog Ethernet VIP to complement its 112G high-speed SerDes PHY IP to enable high-performance cloud computing. It is claimed to be the industry’s first verification IP (VIP) and Universal Verification Methodology (UVM) source code test suite for Ethernet 800G.

The Synopsys VC VIP for Ethernet 800G is based on the Ethernet Technology Consortium (ETC) specification. It enables SoC teams to design next-generation networking chips for data centres with ease of use and fast integration, to accelerate verification closure and time-to-market. The VC VIP is used to verify Synopsys’ DesignWare 56G Ethernet, 112G Ethernet, and 112G USR/XSR PHYs for FinFET processes, which designers can integrate into 800G SoCs.

The ETC standard provides specifications for an 800G implementation based on eight lane x 100Gbits per second technology, enabling adopters to deploy advanced high bandwidth interoperable Ethernet technologies.

Francois Balay, president of MorethanIP, believes the Synopsys VC VIP will prove an advantage to developers. “Being first in the industry, Synopsys VIP, source code test suite and DesignWare IP for Ethernet 800G strengthens the ecosystem and facilitates early adoption of the technology and fast development of high-speed networking applications,” he said.

Synopsys VC VIP for Ethernet uses a native System Verilog UVM architecture, protocol-aware debug and source code test suites. It can switch speed configurations dynamically at run time and includes an extensive and customisable set of frame generation and error injection capabilities. Source code UNH-IOL test suites are available for key Ethernet features and clauses, to facilitate custom testing and accelerate verification closure.

Synopsys VC VIP and source code test suite for Ethernet 800G are both available today as early access standalone products. The DesignWare 56G and 112G Ethernet PHYs are available now and the silicon design kit for the DesignWare USR/XSR PHY IP in 7nm FinFET process is also available.

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